54results about How to "Good component properties" patented technology

The invention discloses a pixel structure, comprising a substrate, a grid, an insulating layer, a metal oxide semiconductor layer, a source, a drain, at least a film layer and a first electrode layer, wherein the grid is positioned on the substrate; the insulating layer covers the grid; the metal oxide semiconductor layer is positioned on the insulating layer above the grid; the source and the drain are positioned on the metal oxide semiconductor layer; the film layer covers the metal oxide semiconductor layer and comprises a transparent photocatalyst material which blocks the light in the ultraviolet light band from penetrating through the metal oxide semiconductor layer; and the first electrode layer is electrically connected with the source or the drain. The invention simultaneously discloses a manufacturing method of the pixel structure and a manufacturing method of an electronic device.

The present invention discloses an array substrate and a method for manufacturing a polycrystalline silicon layer, wherein the method comprises the steps of forming a first buffer layer on a flexible layer, forming a first barrier layer on the first buffer layer, forming a second buffer layer on the first barrier layer, forming a second barrier layer on the second buffer layer, forming an amorphous silicon layer on the second barrier layer, and converting the amorphous silicon layer into the polycrystalline silicon layer through laser.

The invention discloses a thin film transistor and a manufacturing method thereof. The thin film transistor comprises a substrate, a semiconductor layer, a patterning doped semiconductor layer, a source electrode, a drain electrode, a grid isolating layer and a grid electrode, wherein the semiconductor layer is arranged on the substrate; the patterning doped semiconductor layer is arranged above two opposite sides of the semiconductor layer; the source electrode and the drain electrode are arranged on the patterning doped semiconductor layer and above two opposite sides of the semiconductor layer; a part of the semiconductor layer covered by the source electrode and the drain electrode has a first thickness, a part of the semiconductor layer, which is positioned between the source electrode and the drain electrode and not covered by the source electrode and the drain electrode, has a second thickness, and the second thickness is between 200 angstroms and 800 angstroms; the grid isolating layer is arranged on the source electrode, the drain electrode and a part of semiconductor layer; and the grid is arranged on the grid isolating layer. The thin film transistor provided by the invention has better element characteristics.

The invention provides a polycrystalline silicon film making method, using the phenomenon that as an ordinary polycrystalline silicon layer is formed, its surface saliences have different heights, and using partiall higher saliences to generate crystal seeds used in the following crystallizing step, therefore able to make the new formed polycrystalline silicon film have uniform and bigger crystal particles and have fewer lower-density saliences, and further have better surface flatness.

The invention relates to a manufacture method of a storage device. The manufacture method comprises the steps of providing a substrate, wherein the substrate comprises a storage unit area and a peripheral area; forming a plurality of first grid electrodes in the storage unit area and forming at least one second grid electrode in the peripheral area; forming a sacrifice layer on the substrate; forming a first stop layer on the sacrifice layer in the storage unit area; carrying out the etching process by adopting the first stop layer as a mask; sequentially forming a second stop layer on the substrate; depositing a dielectric material on the second stop layer; carrying out the flattening process for the dielectric material by adopting the first stop layer and the second stop layer in the storage unit area as a grinding stop layer; removing the first stop layer and the second stop layer in the storage unit area; removing the sacrifice layer in the storage unit area so as to forming a plurality of first contact openings among the first grid electrodes after the first stop layer and the second stop layer are removed. The stop layers in different thicknesses are formed in the storage unit area and the peripheral area, so that a landing area contacting a plug is not compressed while the size of the storage device is further reduced.

An integrated transformer comprises a first inductor and a second inductor, the first inductor comprises B circles of spiral wirings formed by a first metal layer and A circles of wirings formed by a second metal layer, and the A circles of the wirings formed by the second metal layer is overlapped with the innermost A circles of the wirings of the B circles of the spiral wirings formed by the first metal layer; and the second inductor comprises C circles of wirings formed by at least the second metal layer, the C circles of the wirings, formed by the second metal layer, of the second inductor are substantially overlapped with the partial wirings formed by the first metal layer, A is less than B, and A is less than C.

A display device includes a driving substrate, a plurality of light emitting elements, and a plurality of metal common electrodes. The light emitting elements are dispersively arranged on the drivingsubstrate, and each light emitting element includes an epitaxial structure layer and a first type electrode and a second type electrode arranged on the epitaxial structure layer. A metal common electrode is dispose dispersedly on that drive substrate and contacts a portion of the second type electrode of each light emit element to form an ohmic contact.

The present invention discloses a semiconductor element and a manufacturing method thereof. The manufacturing method comprises the steps of: forming a grid electrode on a substrate; forming a source electrode and a drain electrode above or below the grid electrode; forming a first insulating layer for covering the source electrode and the drain electrode; forming a semiconductor layer between the source electrode and the drain electrode; patterning the first insulating layer for at least covering the drain electrode; forming a second insulating layer on the patterned first insulating layer; etching the second insulating layer to form a second opening which exposes the patterned first insulating layer and is arranged above the drain electrode, wherein, an etching selection ratio, i.e., the second insulating layer/the patterned first insulating layer, is greater than 1; performing wet etching for the patterned first insulating layer via the second opening, so as to form a first opening which is communicated with the second opening and exposes the drain electrode; and forming a pixel electrode which is electrically connected with the drain electrode via the first opening and the second opening.

The invention discloses a production method of a thin film transistor, which comprises the following steps of: providing a base plate firstly; forming a sacrificial layer on the base plate; forming a multicrystal silicon pattern layer on the base plate to surround the sacrificial layer; and then forming a gate insulation layer large enough to cover the multicrystal silicon pattern layer at least. Additionally, a gate pattern is formed on the gate insulation layer above the multicrystal silicon pattern layer and a source electrode region, a drain electrode region and an active region are formed on the multicrystal silicon pattern layer and the active region is positioned between the source electrode region and the drain electrode region. Furthermore, a protection layer is formed to cover the gate pattern and partial gate insulation layer. And then a source electrode conducting layer and a drain electrode conducting layer are formed on the protection layer and electrically connected with the source electrode region and the drain electrode region of the multicrystal silicon pattern layer respectively.