163results about How to "Improve surface flatness" patented technology

A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a through hole and has a surface formed with a plurality of wire-bonding portions, ball-bonding portions and intended-exposing regions. A chip is mounted over the through hole and electrically connected to the wire-bonding portions by a plurality of bonding wires penetrating through the through hole. An encapsulation body encapsulates the chip and bonding wires. The intended-exposing regions serve as a narrow runner which is filled with an encapsulating material forming the encapsulation body, making the encapsulating material not flash over the ball-bonding portions. This allows a plurality of solder balls to be well bonded to the ball-bonding portions, thereby assuring the quality of electrical connection and the surface planarity of the semiconductor package.

Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

The invention relates to a photosensitive polysiloxane composition and a thin film formed by the aforementioned photosensitive polysiloxane composition. The thin film is a planarization film of a TFT substrate, an interlayer insulating film or an overcoat of a core material or a protective material in a waveguide. The invention is to provide a photosensitive polysiloxane composition having excellent surface flatness and high tapered angle of a pattern. The photosensitive polysiloxane composition comprises a polysiloxane (A), an o-naphthoquinone diazide sulfonic acid ester (B), an alkali-soluble resin containing a silyl group (C) and a solvent (D).

In an electro-optic light modulator requiring an electro-optical sensor material such as polymer dispersed liquid crystal, or PDLC is directly coated on an optical glass substrate with a transparent electrode, such as indium tin oxide (ITO) and an optional layer of passivation coating such as silicon dioxide (SiO₂) on its surface. A thin layer of polymeric adhesive is coated on top of PDLC layer and then this two-layer coating is laminated with a dielectric mirror on a polyester film (Mylar™) preferably with the assistance of a vacuum.

The invention discloses modified polyolefin paper without plant fiber. The modified polyolefin paper is formed by a matrix layer 1 without the plant fiber, a matrix layer 2 without the plant fiber and a matrix layer 3 without the plant fiber which are compounded into a whole, wherein the matrix layer 1 and the matrix layer 3 are prepared by 20 to 30 percent of ethylene-acrylic acid modified copolymer EAA, 45 to 60 percent of metallocene high-density polyethylene mHDPE, and 20 to 25 percent of activated ultrafine inorganic powder respectively, and the matrix layer 2 is prepared by 60 to 90 percent of activated ultrafine inorganic powder, 2 to 5 percent of maleic anhydride and 8 to 35 percent of high-density polyethylene. The modified polyolefin paper has the advantages of good ink receptivity and softness. Therefore, the modified polyolefin paper can be used as industrial paper, packing paper and household paper, can also be used as cultural paper, and enlarges the use range. The modified polyolefin paper has higher foldability and rigidity, has the longitudinal and transverse tearing strength which are superior to those of plant fiber paper, has good surface flattening, good handwriting, and clear printing performance, saves printing ink, has simple production technology, protects forest resources, saves energy sources and water, reduces the discharge of organic chlorides and harmful gas, has no waste, and protects the environment.

The invention discloses a control technological method for the planeness of the surface of an LTCC (low temperature co-fired ceramic) substrate. Specific steps are as follows: preparing raw ceramic sheets for the preparation of an LTCC substrate, and punching circuit through holes with a punch press; tearing off a Mylar film; filling LTCC technological hole metal slurry on the raw ceramic sheets, using a roller to roll the holes so as to evenly press flat the protrusions of the holes filled with the metal slurry, and printing LTCC technological metal conductor slurry on the raw ceramic sheets so as to form a circuit figure; aligning and stacking all the raw ceramic sheets layer by layer, and laminating so as to obtain a large bulk of LTCC raw ceramic blank; and after cutting the large bulk of LTCC raw ceramic blank into circuits in the shape of small blocks, sintering so as to obtain the compact and flat LTCC circuit substrate. Therefore, the technological process of planeness control for the surface of the LTCC substrate is achieved. The method, which is low in cost, simple and effective, is suitable for the development and production of substrates with a complex cavity structure of an embedded chip requiring a lot for surface planeness, and substrates automatically micropackaged in a batch manner.

The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate. The thickness of the buffer film is regulated to be smaller than that of a buffer film which is employed for epitaxially growing the Group III nitride semiconductor on a planar growth substrate uniformly in a direction perpendicular to the growth substrate. The growth temperature is regulated to be lower than a temperature at which the Group III nitride semiconductor is epitaxially grown on a planar growth substrate uniformly in a direction perpendicular to the growth substrate. The growth temperature is preferably 1,020 to 1,100° C. The buffer film employed is an AlN film having a thickness of 150 Å or less.

A method for manufacturing a functional film, including disposing a first ink on a substrate and disposing a second ink on the first ink that has been disposed, the first ink containing at least one of a metal and a metal oxide as a solute, the metal and the metal oxide having a melting point of 900 degrees and above in bulk, upon making the metal and the metal oxide to a particle of having a diameter of from 30 to 150 nm, the particle having a melting point of 255 degrees centigrade and above, and the second ink containing an organic metal salt as a solute.

Disclosed is a glass/resin laminate comprising a glass substrate and a resin layer, wherein the resin layer contains a polyimide that is obtained by polycondensing an aromatic diamine having a benzoxazole structure and an aromatic tetracarboxylic acid anhydride, the difference between the average linear expansion coefficient of the glass substrate and the average linear expansion coefficient of the resin layer for the range of 25-300 DEG C is from -100 10-7/ DEG C to +100 10-7/ DEG C, and the glass substrate forms at least one outermost layer of the laminate.

The invention discloses a polycrystalline silicon film and a preparation method thereof, an array substrate and a display device, belonging to the technical field of semiconductors. The preparation method of the polycrystalline silicon film comprises the following steps of: (1) forming a graphene layer and a noncrystalline silicon layer which are adjacent; and (2) enabling noncrystalline silicon to crystallize and form polycrystalline silicon and obtaining the polycrystalline silicon film. The polycrystalline silicon in the polycrystalline silicon film has the advantages of no pollution and low defect density, the crystal grain size of the polycrystalline silicon is uniform in size, the arrangement is ordered, the crystal grain is larger, and further the surface flatness is better. The speed rate of current carriers in the polycrystalline silicon film prepared by the method is increased, and the element performance of a polycrystalline silicon film transistor is improved.

Paper and an image-recording material support which have high surface planarity and excellent gloss are disclosed. Moreover, an image-recording material is disclosed which uses the image-recording material support and is capable of obtaining high quality image. The paper includes raw paper. The paper satisfies at least one of the following conditions (i) and (ii): (i) the paper has an inner bonding strength of 160 mJ or more specified in Japan Technical Association of the Pulp and Paper Industry No. 54, and an average center surface roughness (SRa) on at least one face of the paper is 0.9 μm or less at a cutoff wavelength of 0.3 mm to 0.4 mm, and (ii) an Oken type smoothness S (second) on the at least one face of the paper, and a density ρ (g/cm³) of the paper satisfy an expression S^1/2/ρ³≧15.

The invention provides a post-welding shaping method for a metal target material. According to the method, a buffer cushion and a cushion block are sequentially arranged above the target material of atarget material assembly, and then pressing shaping is carried out, wherein the hardness of the buffer cushion is 30-60HA, the tensile strength is 50-100kg/cm<2>, the problem that penetrating cracksand a cracking phenomenon easily occur due to a great pressure instantaneously born by the surface of the target material in a shaping process is alleviated well, good protection and buffer effects are acted on the target material, and the yield of the target material is increased; and the target material is heated before shaping and a washer is arranged below a back plate of the target material assembly, so that the shaping efficiency of a shaping machine for the target material is increased and the planeness of the target material after shaping is improved, and a high industrial applicationvalue is achieved.

On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate.

A transparent conductive oxide thin film substrate that has a high level of surface flatness, a method of fabricating the same, and an OLED and photovoltaic cell having the same. The transparent conductive oxide thin film substrate that includes a base substrate, a first transparent conductive oxide thin film formed on the base substrate, the first transparent conductive oxide thin film being treated with a first dopant, and a second transparent conductive oxide thin film formed on the first transparent conductive oxide thin film. The second transparent conductive oxide thin film is treated with a second dopant at a higher concentration than the first dopant. The surface of the second transparent conductive oxide thin film is flatter than the surface of the first transparent conductive oxide thin film.

The present invention discloses a surface treatment process for enhancing both the release rate of metal ions from a sacrificial electrode, and the working life of the electrode. A high density of micro pores are formed on the surface of the sacrificial electrode. Chlorine ions are then implanted into the pores. The chlorine ions prevent a passive film from forming on the sacrificial electrode during use, in which an electric current flows through the sacrificial electrode.

Provided are: a group-III nitride semiconductor epitaxial substrate which exhibits superior surface smoothness while inhibiting crack formation and a problem in which the shape of the EL spectrum thereof forms double peaks; a group-III nitride semiconductor using said substrate; and a production method for these. A group-III nitride semiconductor epitaxial substrate (100) according to the present invention is characterized by being provided with: a substrate (112) in which at least a surface section thereof comprises AlN; an undoped AlN layer (114) formed upon the substrate (112); an Si-doped AlN buffer layer (116) formed upon the undoped AlN layer (114); and a superlattice stacked body (120) formed upon the Si-doped AlN buffer layer (116). The group-III nitride semiconductor epitaxial substrate (100) is further characterized in that the Si-doped AlN buffer layer (116) has an Si concentration of at least 2.0*1019/cm3, and a thickness of 4-10 nm.