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Control technological method for planeness of surface of LTCC substrate

A technology of substrate surface and process method, applied in the direction of multilayer circuit manufacturing, etc., can solve the problem of unevenness in the welding area, achieve the effect of improving surface flatness and low cost

Active Publication Date: 2012-10-10
中国航天科工集团第二研究院二十三所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a process method for controlling the flatness of the LTCC substrate surface, which solves the problem of unevenness in the welding area caused by the protrusion of the metal hole post on the surface of the substrate in the conventional process method

Method used

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Examples

Experimental program
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Embodiment Construction

[0022] A kind of LTCC substrate surface flatness control process method, its specific steps are:

[0023] The first step is to punch holes in the green ceramic sheet

[0024] Prepare the green ceramic sheet required for the preparation of the LTCC substrate, and use a punching machine to punch circuit through holes.

[0025] The second step is to uncover the Mylar film

[0026] Turn over the green ceramic sheet that needs to be printed on the tray with clean Mylar film, press the ruler on a corner of the Mylar film along the direction parallel to the diagonal line of the Mylar film, lift the corner, and follow the straight line The ruler moves diagonally in parallel, the Mylar film is lifted with the ruler, and the raw porcelain has no deformation. During the transfer process of the green ceramic sheet, a 100μm thick plastic sheet is used to support and carry it to prevent deformation.

[0027] Step 3 Via Filling Paste

[0028] Use a screen printing machine to fill the LTC...

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PUM

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Abstract

The invention discloses a control technological method for the planeness of the surface of an LTCC (low temperature co-fired ceramic) substrate. Specific steps are as follows: preparing raw ceramic sheets for the preparation of an LTCC substrate, and punching circuit through holes with a punch press; tearing off a Mylar film; filling LTCC technological hole metal slurry on the raw ceramic sheets, using a roller to roll the holes so as to evenly press flat the protrusions of the holes filled with the metal slurry, and printing LTCC technological metal conductor slurry on the raw ceramic sheets so as to form a circuit figure; aligning and stacking all the raw ceramic sheets layer by layer, and laminating so as to obtain a large bulk of LTCC raw ceramic blank; and after cutting the large bulk of LTCC raw ceramic blank into circuits in the shape of small blocks, sintering so as to obtain the compact and flat LTCC circuit substrate. Therefore, the technological process of planeness control for the surface of the LTCC substrate is achieved. The method, which is low in cost, simple and effective, is suitable for the development and production of substrates with a complex cavity structure of an embedded chip requiring a lot for surface planeness, and substrates automatically micropackaged in a batch manner.

Description

technical field [0001] The invention relates to a process method for controlling the surface flatness, in particular to a process method for controlling the surface roughness of an LTCC substrate. Background technique [0002] The LTCC (Low Temperature Co-fired Ceramic) process is used for the manufacture of high-density multilayer circuit substrates for three-dimensional space vertical wiring of miniaturized MCM microwave / millimeter wave modules / components. After the LTCC substrate is sintered and formed, its surface flatness will affect the microwave characteristics of the circuit, such as grounding performance, microwave loss, surface conductor adhesion, and subsequent assembly effects, especially the assembly of bare chips and the brazing of the substrate, which have very high requirements for flatness. High, this is because the unevenness of the substrate leads to a large solder void rate, which ultimately affects the grounding characteristics of the module. Factors af...

Claims

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Application Information

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IPC IPC(8): H05K3/46
Inventor 方哲张芹周卫
Owner 中国航天科工集团第二研究院二十三所
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