Control technological method for planeness of surface of LTCC substrate

Abstract

The invention discloses a control technological method for the planeness of the surface of an LTCC (low temperature co-fired ceramic) substrate. Specific steps are as follows: preparing raw ceramic sheets for the preparation of an LTCC substrate, and punching circuit through holes with a punch press; tearing off a Mylar film; filling LTCC technological hole metal slurry on the raw ceramic sheets, using a roller to roll the holes so as to evenly press flat the protrusions of the holes filled with the metal slurry, and printing LTCC technological metal conductor slurry on the raw ceramic sheets so as to form a circuit figure; aligning and stacking all the raw ceramic sheets layer by layer, and laminating so as to obtain a large bulk of LTCC raw ceramic blank; and after cutting the large bulk of LTCC raw ceramic blank into circuits in the shape of small blocks, sintering so as to obtain the compact and flat LTCC circuit substrate. Therefore, the technological process of planeness control for the surface of the LTCC substrate is achieved. The method, which is low in cost, simple and effective, is suitable for the development and production of substrates with a complex cavity structure of an embedded chip requiring a lot for surface planeness, and substrates automatically micropackaged in a batch manner.

Description

technical field [0001] The invention relates to a process method for controlling the surface flatness, in particular to a process method for controlling the surface roughness of an LTCC substrate. Background technique [0002] The LTCC (Low Temperature Co-fired Ceramic) process is used for the manufacture of high-density multilayer circuit substrates for three-dimensional space vertical wiring of miniaturized MCM microwave / millimeter wave modules / components. After the LTCC substrate is sintered and formed, its surface flatness will affect the microwave characteristics of the circuit, such as grounding performance, microwave loss, surface conductor adhesion, and subsequent assembly effects, especially the assembly of bare chips and the brazing of the substrate, which have very high requirements for flatness. High, this is because the unevenness of the substrate leads to a large solder void rate, which ultimately affects the grounding characteristics of the module. Factors af...