Shifting register and array substrate grid drive device

A shift register and gate connection technology, applied in static memory, digital memory information, instruments, etc., can solve the problems of reducing stability, changing to low level, and PD point voltage signal attenuation, so as to reduce attenuation, The effect of reducing work loss and improving stability

Inactive Publication Date: 2015-06-10
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the prior art, a shift register is composed of a circuit structure of each GOA unit in multiple shift registers. figure 1 As shown, however, when CLKB is high, the gate of M5 is high, M5 is turned on, the PDCN node is high, the gate and drain of M6 are both high, M6 is turned on, and the node PD The point will be in the charging process and become high level; when CLKB is low level, because of the delay effect of M5, the gate of M6 is still high level, but the source of M6 is extremely low level, so that the node PD point and CLKB is directly connected, and at this time CLKB is low level, so the PD point will be in the discharge process and become low level
The periodic charging and discharging process increases the working loss of the shift register. At the same time, after passing through several GOA units, the waveform delay of CLKB is more serious, and the voltage signal of the PD point is seriously attenuated, thus affecting the quality of the display screen.
[0004] To sum up, the shift register provided by the prior art increases the operating loss of the shift register, seriously attenuates the voltage signal at the PD point, and reduces the stability of its operation.

Method used

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  • Shifting register and array substrate grid drive device
  • Shifting register and array substrate grid drive device
  • Shifting register and array substrate grid drive device

Examples

Experimental program
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Embodiment 1

[0051] see figure 2 , a shift register provided by an embodiment of the present invention, wherein the same shift register unit is connected in multiple stages, and the shift register unit includes:

[0052] The input module 201, in response to the input signal INTPUT, is used to provide the first clock signal voltage CLK1 to the pull-up node PU point, wherein the pull-up node is an output node of the input module; including:

[0053] The gate of the first thin film transistor M1 is connected to the input signal terminal, the source is connected to the first clock signal terminal, and the drain is used as the output node of the input module, that is, as the pull-up node PU point;

[0054] The first capacitor C1 is connected between the drain of the first thin film transistor and the first clock signal terminal CLK1;

[0055] The output module 202, in response to the pull-up node PU, is used to provide the second clock signal voltage CLK2 to the output terminal OUTPUT; includ...

Embodiment 2

[0085] see Figure 4 , a cascaded structure diagram of an array substrate gate driving device provided by an embodiment of the present invention, wherein the shift register unit of the cascaded structure takes the shift register provided in Embodiment 1 as an example, wherein,

[0086] If the entire gate drive circuit has a total of N levels of shift register units (GOA units), N is the number of gate lines, and the INPUT of the first level is provided by the vertical turn-on signal (Start Vertical, STV), and the RESET signal of the first level Provided by the OUTPUT of the second stage, the INPUT of the Nth stage is provided by the output of the N-1 stage, and the RESET signal of the Nth stage is provided by the RESET unit. For example, the input signal INTPUT of the nth stage (1

[0087]In summary, in the shift register provi...

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Abstract

The invention provides a shifting register and an array substrate grid drive device. The shifting register is of a structure for multi-stage connection of the same shifting register units, wherein each shifting register unit comprises an input module responding to an input signal, an output module responding to an upward pull node, a reset module responding to a reset signal, a first upward pull module responding to a first clock signal, a second upward pull module responding to a downward pull node voltage signal, a first downward pull module responding to a first upward pull node voltage signal, a second downward pull module responding to an upward pull node voltage signal, a control module responding to a second clock signal and a retaining module responding to the first clock signal and a second downward pull node. The working loss of the shifting register can be reduced, attenuation of a second downward pull voltage signal is reduced, and accordingly the stability of the shifting register in working is improved.

Description

technical field [0001] The invention relates to the technical field of liquid crystal display driving, in particular to a shift register and an array substrate gate driving device. Background technique [0002] Shift registers are used in most flat panel displays, and are implemented by integrating gate drive devices into liquid crystal panels. In recent years, the shift register (Gate on Array, GOA) technology has been widely used in liquid crystal display panels, so people have higher and higher requirements on the service life of the GOA, the work consumption of the GOA, and the stability of the GOA work. [0003] In the prior art, a shift register is composed of a circuit structure of each GOA unit in multiple shift registers. figure 1 As shown, however, when CLKB is high, the gate of M5 is high, M5 is turned on, the PDCN node is high, the gate and drain of M6 are both high, M6 is turned on, and the node PD The point will be in the charging process and become high leve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36G11C19/28
Inventor 王峥
Owner BOE TECH GRP CO LTD
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