Low-power internal clock gated cell and method

Abstract

A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application Serial No. 61 / 913,986, filed December 10, 2013, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to low power internal clock gating units and methods. Background technique [0004] The disclosed circuits and methods relate to integrated circuits. More specifically, the disclosed circuits and methods relate to clock gating cells for integrated circuits. Clock gating units are commonly included in many system-on-chip ("SOC") architectures to reduce the power consumed by the system. However, many conventional clock gating cells are inefficient and consume considerable power themselves. Contents of the invention [0005] In order to solve the problems in the prior art, the present invention provides a circuit, including: a clock trigger block configured to receive a clock signa...

AI Technical Summary

Problems solved by technology

However, many traditional clock gating cells are inefficient and themselves consume considerable power

Images