Spurious reads during read-write collisions to prevent transient open-circuit currents in memory arrays with cross-coupled bit-line keepers

Abstract

The present invention provides systems and methods for detecting and suppressing transient open circuit currents in a memory array (200). Dummy reads are implemented to prevent transient open circuit currents in the event of simultaneous read write collisions in static random access memory SRAM arrays with cross-coupled bit line holders (208a-b). When simultaneous read and write operations to a first entry (202i) of the memory array are detected, the read operation to the first entry (206i) is suppressed and a read operation to the memory array is performed Dummy read operation (206j) for the second entry (202j). The write operation to the first entry is allowed to proceed undisturbed (204i).

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] This patent application asserts a patent filed on October 31, 2012 entitled "DUMMY READ TO PREVENT CROWBAR CURRENT DURING DURING READ-WRITE COLLISIONS IN A MEMORY ARRAY HAVING CROSS-COUPLED CROWBAR CURRENT DURING READ-WRITE COLLISIONS IN MEMORY ARRAYS WITH CROSS-COUPLED KEEPERS)", which is assigned to the present assignee and is hereby expressly and by reference into this article. technical field [0003] The disclosed embodiments relate to managing and preventing transient open circuit currents in memory arrays. More specifically, exemplary embodiments relate to preventing transients due to read-write collisions in memory arrays (e.g., static random access memories (SRAMs)) that include cross-coupled bit line keepers by performing dummy read operations. open circuit current. Background technique [0004] Some processors may allow simultaneous read and write operations to memory structures, such as cache memory, in o...

AI Technical Summary

Problems solved by technology

However, such detection and prevention of conflicts in software is not feasible or practical because programmers may not have sufficient visibility into physical memory locations and / or may lack access to reads as they execute on real-time applications. Control of fetch / write operations

Additionally, this level of software intervention can severely slow down high-performance processing applications

The problem is further complicated when multiple processors share the same memory structure

In an attempt to handle situations where read-write conflicts may occur, existing approaches often rely on expensive and inefficient solutions such as dedicated write buffers

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