Method and apparatus for repairing hold time violations in circuit

Abstract

The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input / output pin thereof.

Description

technical field [0001] The invention relates to the field of circuit design, in particular to a method and device for repairing hold time violations in a circuit. Background technique [0002] When designing a circuit (such as an integrated circuit, etc.), after completing the placement and wiring of various components of the circuit (such as various gate circuits and various standard cells), a timing analysis is performed on the circuit to check whether the circuit There is a timing violation. The timing violation includes setup time violation (setup time violation), hold time violation (hold time violation) and the like. Setup time is the time that the data at the input port of a gate should remain stable before the clock edge reaches the gate. A setup time violation occurs if the data at the input port of the gate remains stable for less than the required setup time, which will result in the data not entering the gate correctly when the clock edge arrives at the gate. ...

AI Technical Summary

Problems solved by technology

However, there are several problems with traditional hold time violation fixes

First, as the size and complexity of circuits increase, the circuits contain a large number of components, making certain areas of the circuit very dense in components, and, in such areas, the variation in the characteristics of the components caused by the manufacturing process (variation) The impact is also relatively large, so there may be a large number of hold time violations

Inserting delay elements in these areas to fix hold violations will further increase the component density in these areas and congest the routing of circuit elements

Additionally, traditional hold fix methods often require moving already placed components and / or their I / O pins, making it easy to create new timing violations

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