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Method, apparatus and system for controlling power consumption of unused hardware of a link interface

A hardware and link technology applied in the field of computing systems

Active Publication Date: 2018-04-13
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, servers demand high performance, while mobile ecosystems are sometimes able to sacrifice overall performance for power savings

Method used

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  • Method, apparatus and system for controlling power consumption of unused hardware of a link interface
  • Method, apparatus and system for controlling power consumption of unused hardware of a link interface
  • Method, apparatus and system for controlling power consumption of unused hardware of a link interface

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Embodiment Construction

[0019] Various specific details are set forth in the description below, such as specific types of processor and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / altitude, Examples of specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known components and methods, such as specific and alternative processor architectures, specific logic circuits / code for the described algorithms, specific firmware code, specific Interconnect operations, specific logic configurations, specific fabrication techniques and materials, specific compiler implementations, specific representation of algorit...

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Abstract

In an embodiment, each of the plurality of hardware buffers may store information associated with one or more virtual channels. In turn, logic is configured for determining an identifier corresponding to a maximum number of virtual channels jointly supported by the first device and the second device coupled via the link, and for obtaining control based on the identifier value. Gate logic coupled to the configuration logic unit is used to provide an operating voltage to a corresponding one of the hardware buffers based on the control value. In this manner, when the maximum number of virtual channels is smaller than the plurality of hardware buffers, the operating voltage can be suppressed from at least one of the hardware buffers. Other embodiments are described and claimed.

Description

technical field [0001] The present disclosure relates to computing systems, and particularly, but not exclusively, to power management of link interfaces in such systems. Background technique [0002] As computing systems evolve, the components within them become more complex. As a result, the interconnect architecture used to couple and communicate between components also increases in complexity in order to ensure that bandwidth requirements for optimal component operation are met. Also, different market segments require different aspects of the interconnection architecture in order to suit the needs of the market. For example, servers require high performance, while mobile ecosystems are sometimes able to sacrifice overall performance for power savings. However, the single purpose of most structures is to provide the highest possible performance with the greatest power savings. Contents of the invention [0003] According to a first aspect of the present invention, th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
CPCG06F13/00G06F1/3253G06F1/3287H04L49/00Y02D10/00G06F15/16G06F1/3234
Inventor V·拉加万
Owner INTEL CORP