Double-track signal wiring method based on wide line

Abstract

The invention discloses a double-track signal wiring method based on a wide line. The double-track signal wiring method comprises the following steps: S1: taking one pair of double-track signal wires as one wide line to carry out wiring; S2: according to the original wire width and the original interval of each layer of metal wire, determining the width obtained after each layer of metal wire is widened; S3: compiling a custom wiring rule, using the wiring rule before clock tree wiring and signal wire wiring are carried out, and obtaining a wide-line single-ended wiring structure; S4) exporting a single-ended DEF file with the routing position and direction information of the wide line, wherein the segmentation of the wide line is realized through script processing, and the processed file has double-track wiring information; and S5) importing the revised DEF file into a design again to obtain a symmetrical wiring structure of a double-track signal wire. The double-track signal wiring method has the advantages of being easy in implementation and low in design complexity and exhibits capacitance symmetry.

Description

technical field [0001] The invention mainly relates to the field of IC testing, in particular to a double-track signal wiring method based on wide lines. Background technique [0002] Since the dynamic power consumption of the circuit is directly proportional to the load capacitance at the output end, it is necessary to ensure that the complementary output ends have symmetrical capacitive loads in order to achieve power balance. The capacitive load at the output of the logic cell consists of the parasitic capacitance of the interconnect lines and the input capacitance of the fanout logic. The shape and length of the interconnect and the different metal layers used for the interconnect will cause a large difference in parasitic capacitance. As the process of integrated circuit design and manufacturing becomes more and more complex and the process size is continuously reduced, the influence of parasitic capacitance is increasing; at the same time, the existing EDA tools do no...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the clock tree is copied into two copies, and the increase will cause a large power consumption overhead

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