Chip screening method and apparatus

A screening method and chip technology, applied in the field of communication, can solve problems such as high cost, low reliability, and high subjectivity, and achieve the effect of reducing screening cost and high reliability
CN105095618AActive Publication Date: 2015-11-25HUAWEI TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUAWEI TECH CO LTD
Publication Date
2015-11-25

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Abstract

The present invention provides a chip screening method and apparatus. The method comprises: calculating a first influence factor of each chip within a peripheral range of a to-be-determined chip, and summing the first influence factors of the chips within the peripheral range to obtain a sum of the influence factors; normalizing the first influence factor of each chip within the peripheral range based on the sum of the influence factors to obtain a second influence factor; summing the second influence factors of effective chips within the peripheral range to obtain a correlation factor NDCF of the peripheral chips of the to-be-determined chip; and if the NDCF of the to-be-determined chip meets predefined screening criteria, determining that the to-be-determined chip is a chip with a large potential failure rate. The present invention reduces chip screening costs.
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Description

technical field

[0001] The embodiments of the present invention relate to communication technologies, and in particular to a chip screening method and device. Background technique

[0002] The Factory Defective Parts Per Million (FDPPM) requirement for carrier-grade products is usually high. How to improve the quality of shipments and reduce the FDPPM of chips is the primary issue for manufacturers to improve profitability and customer satisfaction. One of the main reasons for the high FDPPM is the high early failure rate (Early Failure Rate, referred to as: EFR) of the chip. Screening out chips that may cause potential failure risks in the mass production test of the chip is a method to reduce the EFR. For example, a chip that is judged as a FailDie in the wafer test, although the surrounding PassDie can meet the wafer test specifications, the probability of early failure of these passDie chips is higher than that of passDie in other locations. , that is, the potential ris...

Claims

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