Method and apparatus for realizing flow statistics of network chip efficiently

Abstract

The invention discloses a method and apparatus for realizing flow statistics of a network chip efficiently. The method comprises: an ACL flow table in a chip is searched based on a message, a matched flow table is found out and a flow statistics behavior is associated; according to the associated flow statistics behavior, information in an RAM internal memory is updated; and a DMA controller carried out the following steps periodically: statistic data in the RAM internal memory are read regularly and the data in a DAM internal memory are read simultaneously, the read statistic data in the RAM internal memory and the read data in the DMA internal memory are accumulated and then are written back in the DMA internal memory. The DMA internal memory is a CPU internal memory of a designated address allocated for the chip DMA by the CPU. According to the invention, statistics synchronization and accumulation to the CPU internal memory are realized completely by the chip DMA and software participation during the whole process is not required; the CPU occupancy rate is substantially reduced; and the flow stats function can be completed efficiently.

Description

technical field [0001] The invention relates to a flow statistics technology, in particular to a method and device for efficiently realizing network chip flow statistics. Background technique [0002] Flowstats (traffic statistics) is a technology that relies on ACL (Access Control List) to realize traffic statistics, and is widely used in traffic analysis and problem location. Identify specific flows based on the ACL and associate them with stats entries, and collect statistics on the identified flows into the stats entries. Stats entries are implemented using physical memory in the chip, and the specifications of the entries are limited. In order to prevent statistical inversion caused by overflow, most of the existing chips set the threshold, and when the threshold is reached, an interrupt will be triggered. At this time, the cpu (central processing unit) takes over the interrupt and reads the stats in the chip ram (random access memory). Statistics, and cleared to 0. T...

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Problems solved by technology

[0003] Since the stats entry occupies ram resources, it is impossible to set too much bit width. Calculated according to the traffic of 100G, the packet statistics in 1s need to occupy 34 bits of ram resources, and the interruption needs to be at least once every 1s to be effective. In this case, the impact on the cpu is very large, and the efficiency is very low

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