Fixed-bit-width multiplier with high accuracy and low energy consumption properties

Abstract

The present invention relates to the technical field of integrated circuits, and in particular to a fixed-bit-width multiplier with high accuracy and low energy consumption properties. The fixed-bit-width multiplier with the high accuracy and low energy consumption properties comprises a CSD encode circuit, a high position partial product generation circuit, a low position compensation circuit and a partial product compression circuit, wherein an input port of the CSD encode circuit is connected to external input data, and an output port of the CSD encode circuit is connected to the high position partial product generation circuit and the low position compensation circuit; the high position partial product generation circuit is connected to the external input data, and an output port of the high position partial product generation circuit is connected to the partial product compression circuit; the low position compensation circuit is connected to the external input data, and an output port of the low position compensation circuit is connected to the partial product compression circuit; and an output port of the partial product compression circuit is connected to the external input data. The present invention has the beneficial effects that a fixed-bit-width multiplier with low energy consumption and a relatively high speed, and a practical fixed-bit-width multiplier design with high accuracy and low energy consumption are achieved. The fixed-bit-width multiplier of the present invention is particularly suitable for implementation of a high-accuracy multiplication with low energy consumption and a fixed bit width.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a fixed bit width multiplier with high precision and low energy consumption. Background technique [0002] The multiplier is a very important basic unit in digital integrated circuits. In digital system design, the performance and power consumption of the multiplier largely affect the entire digital system. [0003] In the multiplier design, the encoding circuit is generally used to encode the multiplier to reduce the number of non-zero bits in the multiplier to reduce the generation of partial products, and then reduce the number of adders used to accumulate partial products to simplify hardware. The purpose of reducing power consumption and increasing the speed of multiplication. Among them, the CSD (CanonicalSignedDigit) encoder is a redundant signed number encoding method applied to multiplication operations. Its advantage is that it can minimize the...

AI Technical Summary

Problems solved by technology

The full-precision calculation and truncation method is to truncate the digits with lower weight on the result of the full-precision calculation, and then use the constant compensation method to achieve higher precision, but its power consumption and speed are not superior to the full-precision design. ; Although the direct truncation method has lower power consumption and faster speed, the calculation result has a larger error than the accurate result, so the application value is low

The traditional fixed-bit-width CSD multiplier has obvious shortcomings in the design of the compensation method, which greatly restricts the application range of the fixed-bit-width CSD multiplier.

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