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Low cost and anti-interference dual mode laminated design method

A design method and low-cost technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as signal quality degradation and high-speed line crosstalk increase, and achieve the effects of reducing interference, reducing research and development costs, and improving signal quality

Inactive Publication Date: 2015-12-30
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the disadvantage is: compared with the ordinary stack design, there is no GND plane isolation between the signal layers, which increases the crosstalk of high-speed lines and reduces the signal quality
However, in the case of dualstripline mode, in order to reduce crosstalk between signals and meet signal integrity requirements, there are great challenges and requirements for the layout of high-speed signal lines

Method used

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  • Low cost and anti-interference dual mode laminated design method
  • Low cost and anti-interference dual mode laminated design method

Examples

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Effect test

Embodiment 1

[0023] Such as figure 2 As shown, a low-cost and anti-interference dual mode stack design method. In the dualstripline mode stack design, when two adjacent signal layers are simultaneously wired with high-speed signal lines, the same area of ​​the PP layer is added at the same position core to isolate the two layers of signal interference.

[0024] The traditional 12-layer board is laminated with 6 signal layers, such as figure 1 As shown, it is designed as a 12-layer board with 8 signal layers dual mode stacks, such as figure 2 As shown, when two adjacent signal layers are simultaneously wired with high-speed signal lines, a core of the same area is added at the same position on the PP layer to isolate the signal interference of the two layers.

Embodiment 2

[0026] On the basis of embodiment 1, when the method described in this embodiment does not have a high-speed signal line in two adjacent signal layers, only the PP layer is provided to reduce the usage of the core to reduce the cost.

Embodiment 3

[0028] On the basis of Embodiment 1, when the method described in this embodiment has only one layer of high-speed signal lines on two adjacent signal layers, only the PP layer is provided, which reduces the usage of cores to reduce costs.

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Abstract

The invention discloses a low cost and anti-interference dual mode laminated design method. When two adjacent layers of signal layers are distributed with high-speed signal wires at the same time in a dual strip line mode laminated design, two layers of signals are isolated to disturb by adding cores with same areas on the same positions of polypropylene (PP) layers. The low cost and anti-interference dual mode laminated design method can reduce development cost, reduces interference between two adjacent signal layers simultaneously, and improves signal quality.

Description

Technical field [0001] The invention relates to the technical field of server motherboard design, in particular to a low-cost and anti-interference dual mode stacking design method. Background technique [0002] With the advent of cloud computing, the development of servers has risen rapidly. In the design of servers, signal speeds are getting higher and higher, and the space design requirements and costs of high-speed signals for motherboards are also increasing. Therefore, in the stacked design, the dualstripline mode is favored by designers. [0003] The laminated design of dualstripline mode is different from the ordinary laminated design. The characteristic of the laminated design is that the two signal layers are designed as adjacent layers. [0004] The laminated design of dualstripline mode uses two adjacent signal layer wiring, which can reduce the design cost, but there is no GND layer shielding between the signal layers, and the crosstalk between the signal layers is rela...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 张春丽李永翠
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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