Semiconductor packaging mold, packaging structure and packaging method

Abstract

The invention discloses a semiconductor package mold, a package structure and a package method. The encapsulation mold includes a lower mold and an upper mold inverted on the lower mold, the lower surface of the upper mold and the upper surface of the lower mold are formed as concave-convex matching curved surfaces. The packaging mold and packaging method of the present invention can effectively reduce the warpage caused by the thermal mismatch between the packaging layer and the substrate.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a semiconductor packaging mold, a packaging structure and a packaging method. Background technique [0002] Semiconductor packaging technology has the functions of providing electrical connection, protection, support, and heat dissipation for chips. It can realize multi-pin, and has the advantages of reducing the volume of packaged products, improving electrical performance and heat dissipation, ultra-high density or multi-chip modularization. Most of the existing semiconductor packages need to bond or bond the chip to the substrate, and then package it with a mold. [0003] Figure 1a-Figure 1c is a schematic diagram of a packaging mold used in conventional semiconductor packaging technology (in which injection holes and positioning holes are ignored). like Figure 1a-Figure 1c As shown, the conventional packaging mold includes an upper mold 101 and a lower mold 102, the lo...

AI Technical Summary

Problems solved by technology

[0004] Due to the difference in the coefficient of thermal expansion (CTE) between the encapsulation layer material (for example, epoxy molding compound (EMC)) and the substrate material (for example, FR4 or BT) (for example, a certain EMC has a coefficient of thermal expansion (CTE) of 45ppm, while for The thermal expansion coefficient of FR4 of the substrate is 18ppm), which causes the expansion or contraction volume of the encapsulation layer and the substrate to be unequal when the temperature rises and falls, which easily causes warpage

The generation of warpage can cause the breakage of the chip, and also cause failures such as open circuit (OPEN) or pillow effect (HiP) in the subsequent assembly process (such as SMT)

This phenomenon is very common and increases the production cost and reduces the reliability of the package structure

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