Multi-modulus frequency divider

Abstract

A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider.

Description

technical field [0001] The invention relates to a frequency divider. Background technique [0002] Modern communication ICs often integrate high-frequency circuits to generate local oscillators for receiving and transmitting data. The most common architectures include LC-VCO (Voltage Controlled Oscillator with LC Tank), where a high-frequency signal is used in a PLL to generate an accurate, low-noise clock signal. The oscillation frequency of a VCO is usually higher since it allows a compact design of the LC tank and achieves lower noise through subsequent frequency division. [0003] The circuits that feed the signal output from the VCO into the PLL are typically sensitive, power-hungry buffers or frequency dividers. The main difficulty in designing such a circuit is that the required direct connection to the resonant tank of the VCO may lead to quality, noise degradation, while affecting the center frequency of the VCO. Additionally, signal common-mode at the VCO output...

AI Technical Summary

Problems solved by technology

These additional circuits may cause performance degradation of the frequency divider and the VCO itself

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