Chip failure analysis method

Abstract

The application discloses a chip failure analysis method, the failure analysis method includes: locating the through-silicon hole structure in the chip that generates leakage current; grinding the chip along the direction perpendicular to the surface of the chip until it is close to the through-silicon hole structure. The vertical cross-section of the upper surface; the marking points are sequentially set at intervals on the cross-section; a test voltage is applied between the TSV structure and the substrate in the chip to obtain the leakage current position of the TSV structure, and place it on the horizontal The corresponding position on the cross-section is marked as a hot spot; the two marker points adjacent to the hot spot are marked as the first marker point and the second marker point, and the leak is located by the depth relationship between the hot spot and the first marker point and the second marker point. depth of current. This method can accurately obtain the depth position of the leakage current in the chip, and then effectively guide the subsequent physical failure analysis method and process improvement. At the same time, the machines used in this method are all existing traditional machines, and there is no need to increase the machine budget.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, in particular, to a chip failure analysis method. Background technique [0002] In the manufacturing process of a chip (3D IC), it is necessary to stack the chips in three-dimensional directions through a through-silicon via structure (TSV) to make a chip with powerful performance and high cost efficiency. However, since the TSV structure is very deep (generally 100 μm), leakage current is easily generated near the bottom of the TSV structure (about 100 μm in depth), thereby degrading the performance of the chip. Therefore, in the process of improving chip yield, engineers need to perform failure analysis (FA) on the chip to find out where the leakage current occurs in the chip, and then use the physical failure analysis method (PFA) to analyze the cause of the leakage current, so that Subsequent improvements to the chip. [0003] At present, the position of ...

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Problems solved by technology

However, the depth accuracy obtained by this kind of simulation calculation is not high. Generally, the depth accuracy is only about 20 μm (for example, it can only be determined that the hot spot is within the range of 0-20um below the TSV structure, or it can only be determined that the hot spot is in the silicon via structure. The through-hole structure is within the range of 20-40um down, etc.)

In addition, this FA machine is expensive, which limits its application in the field of hot spot detection

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