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A Synchronization Method for Software-Hardware Co-simulation

A technology of software and hardware collaboration and event triggering, applied in software simulation/interpretation/simulation, instruments, calculations, etc., can solve the problem of long time-consuming recording of waveforms, inability to make continuity test cases, and inability of verifiers to know and make decisions in time Check and other issues to achieve the effect of reducing the programming burden

Active Publication Date: 2018-10-26
RAMAXEL TECH SHENZHEN
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Problems solved by technology

Since the current verification method and platform cannot directly know the execution status of the CPU code, the verification personnel cannot be informed and checked in time
The current common practice is to execute the software code on the CPU and record the waveform through the emulator to complete the inspection. The disadvantage of this method is that the recorded waveform needs to be manually inspected, which cannot be automated, and it takes a long time to record the waveform. do a lot of testing
Another popular solution is that in a test case, the CPU only performs one operation, and the verifier waits for a specific time based on experience to check. The disadvantage of this approach is also obvious: a test case can only be completed. Minimized simple checks, unable to make complex continuity test cases due to the uncertainty of waiting time

Method used

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  • A Synchronization Method for Software-Hardware Co-simulation

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Embodiment Construction

[0009] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0010] figure 1 It is a system block diagram of the synchronization method of software and hardware co-simulation. The CPU to be verified is connected to the verification platform through a bus. It is characterized in that a trigger event address space is reserved in the CPU to be verified. The virtual address Dummy Address that coincides with the actual address of the CPU internal register and memory to be verified; the trigger event address space is divided into ...

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Abstract

The present invention discloses a synchronization method for software and hardware collaborative simulation. The method comprises writing specific data to a dummy address through a to-be-verified CPU; a bus functional module of a verification platform receiving related information; and a decoding module parsing a specific event of the data. A methodological callback is used to correspond with each event. When a chip verifier develops a test case, synchronization can be completed only by adding a code for triggering the CPU to write code to the dummy address, then inheriting a callback corresponding to the event in the methodology. According to the method provided by the present invention, a code execution status of the to-be-verified CPU can be real-time monitored; a real-time inspection is performed by synchronization; the method is applicable to a test case with a complex structure, and combines a callback of verification methodology; so that a programming burden of a verifier can be reduced.

Description

technical field [0001] The invention relates to the field of chip verification, in particular to a method for synchronizing software codes executed on a CPU to be verified and software and hardware co-simulation of a chip verification platform. Background technique [0002] In the current system-level verification, it is often necessary to execute software codes in the CPU to verify the functions and reliability of the system. For example, the CPU executes a specific code to complete the configuration of a certain function of the chip. When the verification personnel need to check whether the configuration set by the CPU is effective, they need to write specific code in the verification platform to check. Since the current verification method and platform cannot directly know the execution status of the CPU code, verification personnel cannot be informed and checked in time. The current common practice is to execute the software code on the CPU and record the waveform throu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/455
CPCG06F9/45508
Inventor 赵胜平张鹏
Owner RAMAXEL TECH SHENZHEN
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