Synchronous test method and system supporting multiple PCIE cards

A technology for synchronous testing and testing hosts, applied in the testing field, can solve problems such as single test content and low efficiency, and achieve the effects of avoiding false tests, reducing test times, and wide applicability

Active Publication Date: 2021-02-26
ZHENGZHOU XINDA JIEAN INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Aiming at the problems of low efficiency and single test content of the traditional PCIE card test method, the present invention provides a synchronous test method and system supporting multiple PCIE cards

Method used

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  • Synchronous test method and system supporting multiple PCIE cards
  • Synchronous test method and system supporting multiple PCIE cards

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Experimental program
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Effect test

Embodiment 1

[0051] like figure 1 As shown, the embodiment of the present invention provides a kind of synchronous testing method that supports a plurality of PCIE cards, and described method comprises the following steps:

[0052] S101: Insert a plurality of PCIE cards on the test host through physical interfaces, wherein each PCIE card includes a plurality of DMA high-speed channels, a plurality of BAR low-speed channels and a configuration space, and the configuration space is used to store PCIE card identification information , the number of DMA high-speed channels, the number of BAR low-speed channels;

[0053] S102: The operating system of the test host monitors that multiple PCIE cards are connected, and then starts multiple test processes respectively, and the multiple test processes correspond to multiple PCIE cards one by one;

[0054] S103: Under each test process, start the PCIE card configuration space monitoring thread, and identify the PCIE card identification information, ...

Embodiment 2

[0060] On the basis of the above-mentioned embodiment 1, the difference between the embodiment of the present invention and the above-mentioned embodiment is that this embodiment further optimizes the test process in step S105, and each DMA test thread group includes A DMA sending thread for channel sending test data and a DMA receiving thread for receiving response data, each BAR test thread group includes a BAR sending thread for sending test data to the BAR low-speed channel and a BAR receiving thread for receiving response data, Specifically:

[0061] S1051: The DMA sending thread sends the DMA test data to the corresponding DMA high-speed channel, and the BAR sending thread sends the BAR test data to the corresponding BAR low-speed channel;

[0062] S1052: After the corresponding DMA high-speed channel receives the DMA test data and performs transparent transmission or processing, returns the DMA response data to the corresponding DMA receiving thread; at the same time, t...

Embodiment 3

[0065] In order to test the limit speed of each PCIE card, the embodiment of the present invention also provides a kind of synchronous testing method that supports a plurality of PCIE cards, and the difference with each above-mentioned embodiment is that the present embodiment also includes the following steps:

[0066] S107: After determining that the data processing performance of the PCIE card is qualified, test the limit speed of each DMA high-speed channel through each DMA test thread group corresponding to the test process, and test the limit of each BAR low-speed channel through each BAR test thread group speed.

[0067] As a kind of implementable mode, the limit speed of each DMA high-speed channel is tested respectively by each DMA test thread group corresponding to the test process, specifically including:

[0068] S1071: The DMA sending thread repeatedly sends DMA test data to the corresponding DMA high-speed channel according to the preset initial frequency, and ma...

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PUM

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Abstract

The invention provides a synchronous test method and system supporting multiple PCIE cards. The method comprises the following steps: respectively inserting a plurality of PCIE cards into a test hostthrough physical interfaces; when an operating system of the test host monitors that a plurality of PCIE cards are accessed, respectively starting a plurality of test processes; under each test process, starting a PCIE card configuration space monitoring thread; starting a plurality of DMA test thread groups by each test process based on the number of the DMA high-speed channels, and starting a plurality of BAR test thread groups based on the number of the BAR low-speed channels; under each test process, asynchronously testing the data processing accuracy of each DMA high-speed channel and each BAR low-speed channel through a plurality of DMA test thread groups and BAR test thread groups; and for each PCIE card, if a test thread group exceeding a preset threshold feeds back a DMA high-speed channel or BAR low-speed channel data processing error, judging that the data processing performance of the PCIE card is unqualified, and otherwise, judging that the performance is qualified.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a synchronous testing method and system supporting multiple PCIE cards. Background technique [0002] At present, many hardware devices (such as PCIE cards) need to be tested for performance after the development is completed. Since PCIE cards are usually equipped with multiple DMA high-speed channels and BAR low-speed channels, when testing the performance of PCIE cards, not only the limit speed of a single DMA channel, but also multiple DMA high-speed channels and multiple BARs need to be considered. Stability in low-speed channel parallel mixed scenarios requires higher testing requirements for a single PCIE card. In addition, the traditional test method can only realize the test of a single PCIE card at a time. However, in actual scenarios, there may be many PCIE cards that need to be tested, and it is necessary to repeat multiple tests to complete, and the test efficiency ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22
CPCG06F11/2221G06F11/2273
Inventor 王斌王中原吴世勇李银龙冯驰王凯霖
Owner ZHENGZHOU XINDA JIEAN INFORMATION TECH
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