A connection method and system for rate-configurable FPGA inter-chip communication

Abstract

The present invention provides a connecting method and system for communication between rate configurable FPGA chips. The method comprises: connecting two FPGA chips through Gigabit transceivers respectively configured in the two FPGA chips. Each of the FPGA chips is configured with a connection state write register and a channel rate write register, which are respectively used for controlling channel connection states and channel rates in respective FPGA chips according to received external input instructions, while controlling the matching with data transmission rates of the respective FPGA chips receiving and transmitting data, thereby finally realizing switching control of inter-board data links. According to the connecting method and system, high and low-rate data transmission modes are compatible, and different rate modes are independent of each other and non-interfering; and a design verification mode compatible with high and low rates can set up a plurality of test environments at the same time to perform verification, cause no influence on transmission performance for change of a rate mode, effectively shorten a design verification period and reduce costs.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to the field of FPGA communication technology, in particular to a connection method and system for rate-configurable FPGA interchip communication. Background technique [0002] With the development of large-scale integrated circuits, the data transmission rate is also increasing. The parallel I / O interface represented by the traditional PCI bus technology can no longer meet the needs of the network and user terminals for the communication bandwidth of the high-speed I / O interface. Serial communication technology becomes mainstream. [0003] The serial communication technology represented by Serdes reduces the number of required channels and device pins, and the single-channel communication capability can reach 28Gbps. This technology puts forward higher requirements for the board-level verification scheme in the chip design process. One verification scheme is to connect the high-spee...

AI Technical Summary

Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a connection method and system for inter-chip communication of a rate configurable FPGA, which is used to solve the problems of long cycle and low verification efficiency in FPGA test verification in the prior art. question

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