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A kind of usb interface based on pcie bus and its realization method

A USB interface, USB3.0 technology, applied in the field of USB interface and implementation based on PCIE bus, to achieve the effect of high data processing efficiency, fast data transmission speed, and bidirectional transmission

Active Publication Date: 2018-10-19
TOEC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can be seen that the use of PCIE has great limitations, and greater expansion is needed

Method used

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  • A kind of usb interface based on pcie bus and its realization method

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Embodiment Construction

[0012] like figure 1 As shown, the USB interface based on the PCIE bus includes a USB3.0 interface J2, and also includes a PCIE general-purpose chip J1.

[0013] PCIE universal chip J1 includes clock line CLK_PCIE-, clock line CLK_PCIE+, data receiving line PCIE_RX0-, data receiving line PCIE_RX0+, data transmitting line PCIE_TX0-, data transmitting line PCIE_TX0+, and three grounding lines GND_POWER.

[0014] The USB3.0 interface J2 has a total of 11 pins. The 1 pin, 4 pin, and 7 pin of the USB3.0 interface J2 are ground pins, and the 2 pins are connected to the clock line CLK_PCIE- of the PCIE universal chip J1, and the 3 pins Connect the clock line CLK_PCIE+ of the PCIE universal chip J1, 5 pins connect to the data receiving line PCIE_RX0-, 6 pins connect to the data receiving line PCIE_RX0+, 8 pins connect to the data transmitting line PCIE_TX0-, 9 pins connect to the data transmitting line PCIE_TX0+, 10 pins Pin and pin 11 are connected to the ground of the chassis, and ...

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Abstract

The invention relates to a PCIE bus based USB interface and an implementation method. Internal data is sent out along a data transmission line PCIE-TX0+, and a data transmission line PCIE-TX0- of a PCIE universal chip J1 through the ninth pin and the eighth pin of a USB3.0 interface J2; external data is transmitted in along a data receiving line PCIE-RX0-, and a data receiving line PCIE-RX0+ of the PCIE universal chip J1 through the fifth pin and the sixth pin of the USB3.0 interface J2; a clock line CLK-PCIE- and a clock line CLK-PCIE+ provide a reference clock for enabling the data receiving and data transmitting of the USB3.0 interface J2 to be synchronous with a host computer or a single-board computer of the whole system; and the PCIE bus is connected to the USB3.0 universal interface, so that a higher data transmission speed and a higher data processing efficiency are realized, meanwhile, the point-to-point serial connection and data two-way transmission are realized as well.

Description

technical field [0001] The invention relates to a USB interface based on a PCIE bus and an implementation method thereof, which can be used on devices equipped with the PCIE bus protocol and using the USB interface, such as computer hosts and single-board computers. Background technique [0002] PCI-Express (PCIE) is the latest bus and interface standard. It adopts point-to-point serial connection, so that each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, supports bidirectional data transmission, and can increase the data transmission rate raised to a high frequency. The USB3.0 interface is the latest USB specification, and the maximum transmission bandwidth can reach 5.0Gbps. Due to its fast data transmission speed and high data processing efficiency, the USB3.0 interface has also become a necessary interface on mainstream computers and boards. Now, the technical specification of PCIE allows to realize the channel spe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
CPCG06F13/385G06F2213/0024
Inventor 李羚梅云天嵩张鹏泉曹晓冬崔俊鹏苏晓旭杨光蒋航刘政鹏
Owner TOEC TECH