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Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit

A technology of integrated circuits and functional blocks, applied in circuits, CAD circuit design, semiconductor/solid-state device manufacturing, etc.

Active Publication Date: 2016-03-09
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, this solution requires the implementation of the input and output stages in a conventional CMOS structure, thus prohibiting the use of special non-CMOS parts to equip the output stage, for example, for proper characterization over time, or to obtain High input capacitance for input stage

Method used

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  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit

Examples

Experimental program
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Embodiment Construction

[0044] exist figure 1 , reference numeral 1 denotes a portion selected from the layout of the integrated circuit IC.

[0045] In this example, the layout includes three identical pre-characterized cells CEL. Each cell CEL here is a CMOS inverter including an NMOS transistor and a PMOS transistor.

[0046] More precisely, these cells are formed within a semiconductor substrate and are delimited by an insulating region 2, for example of shallow trench isolation (or, STI) type.

[0047]The cell CEL comprises an active semiconductor area region delimited by an insulating region 2, and comprises a first active region 10 (source, channel and drain region) for a first MOS transistor of the inverter, and a region for The second active region 11 of the second MOS transistor of the inverter.

[0048] The cell CEL also comprises a polysilicon region 3 forming the gate regions of the two transistors MOS, and comprises a portion 30 located above the channel region of the first MOS tran...

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Abstract

Various embodiments of the invention relates to a method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and a corresponding integrated circuit. An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and / or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and / or inside of the at least two identical functional blocks.

Description

[0001] priority claim [0002] This application claims priority from French patent application No. 1458099 filed on August 29, 2014, the disclosure of which is incorporated herein by reference. technical field [0003] The present invention relates to integrated circuits and, more particularly, to the manufacture of integrated circuits for the purpose of making reverse engineering of the integrated circuits more difficult. Background technique [0004] Reverse engineering of integrated circuits consists essentially in analyzing integrated circuits in order to determine their internal structure and their operation, for example for copying and duplication. [0005] A key step in the reverse engineering process is the identification of standard cells and the identification of individual components by pattern matching techniques in order to determine the list (or, 'netlist') of interconnect structures and components, and possibly also reconstruct the integrated circuit's layer...

Claims

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Application Information

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IPC IPC(8): H01L21/70H01L27/04H01L23/00
CPCH01L21/70H01L23/57H01L27/04H01L23/573H01L27/0203H01L2924/0002G06F30/39H01L2924/00H01L21/768H01L23/576H01L21/76838
Inventor P·弗纳拉C·里韦罗G·鲍顿
Owner STMICROELECTRONICS SRL