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Floating point fusion multiplication and addition method based on interior forward-push, apparatus and processor

A technology of adding device and floating point, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of long blocking time and low execution speed, so as to reduce the blocking beat, improve the execution speed, reduce the The effect of running water

Inactive Publication Date: 2016-03-16
SUZHOU POWERCORE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved in the present invention is to overcome the defects of long blocking time and low execution speed of the floating point fusion multiplication and addition method in the prior art

Method used

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  • Floating point fusion multiplication and addition method based on interior forward-push, apparatus and processor
  • Floating point fusion multiplication and addition method based on interior forward-push, apparatus and processor
  • Floating point fusion multiplication and addition method based on interior forward-push, apparatus and processor

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Embodiment 1

[0046] This embodiment provides a floating-point fusion multiply-add method based on internal forwarding, for example, it is applied to perform a floating-point fusion multiply-add operation in the form of B×C+A, and the floating-point fusion multiply-add operation can be one instruction (that is, the Instruction execution operation: B×C+A), may also include at least two instructions (such as instruction 1 execution operation: A2=B1×C1+A1, instruction 2 execution operation: A3=B2×C2+A2, instruction 3 execution operation : A4=B3*C3+A3, etc.), so the first product operation hereinafter is, for example, B1*C1, and the second product operation is, for example, B2*C2. Such as figure 2 As shown, the floating-point fusion multiplication-add method includes a five-stage pipeline, including the following steps:

[0047] S1. Execute the first part of compression operations including exponent addition, comparison and selection operations and array multiplication operations in the first...

Embodiment 2

[0082] Corresponding to Embodiment 1, this embodiment provides a floating-point fusion multiplication and addition device based on internal forward push, including:

[0083] The first-stage unit 1 includes an exponent plus ratio selection unit for performing an exponent plus comparison selection operation in the first-stage pipeline and a first part of compression for performing the first part of the compression operation in the first-stage pipeline in the array multiplication operation Unit, the index addition and comparison selection unit includes a first index addition and comparison selection subunit, which is used for the exponent value of the addend in the addition operation and the first product operation when there is no first forward value or second forward value. The exponent value of the first factor and the exponent value of the second factor in the first product operation are subjected to an exponent addition ratio selection operation to generate the first control ...

Embodiment 3

[0100] This embodiment provides a processor, including the floating-point fusion multiplication and addition device in Embodiment 2.

[0101] Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

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Abstract

The invention discloses a floating point fusion multiplication and addition method based on interior forward-push, apparatus and processor. The method comprises five grades of streamlines. Index addition comparison and selection operation and a first part compression operation are executed in a first grade streamline; the index addition comparison and selection operation is conducted according to a first forward-push value and a second forward-push value; the first forward-push value is an index value corresponding to an intermediate result produced by match exponent shifting operation; the second forward-push value is an index value corresponding to an intermediate result produced by leading zero operation; match exponent shifting operation and a second part compression operation are executed in a second grade streamline line; the match exponent shifting operation is conducted according to a third forward-push value; the third forward-push value is an intermediate result produced by addition operation; leading zero operation and addition operation are executed in a third grade streamline; the leading zero operation and the addition operation are conducted according to the third forward-push value; first normalized operation is executed in a fourth grade streamline; and round off operation is executed in a fifth grade streamline. The floating point fusion multiplication and addition method based on interior forward-push is advantaged by short blocking time and quick executing speed.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a method, device and processor for floating point fusion multiplication and addition based on internal forward push. Background technique [0002] A fused multiply-add operation (FMA, FusedMultiply-add) is a floating-point multiply-add operation that performs A+B×C type in one step, and is a common arithmetic operation that only performs rounding once. That is to say, the non-fused multiply-add operation first calculates the result of B×C, rounds the result to N valid bits, then adds the result to A, and finally rounds the result to N valid bits. bit. The fused multiply-add operation calculates the value of A+B×C with full precision, and then rounds the final result to N effective digits. It can be seen that the fusion multiplication and addition operation has the advantages of fast calculation speed and high calculation precision compared with the traditional floating-...

Claims

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Application Information

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IPC IPC(8): G06F7/483G06F7/544
CPCG06F7/483G06F7/5443
Inventor 姚涛李芳曹俊贾琳黎
Owner SUZHOU POWERCORE TECH CO LTD
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