Device and method for improving replay of loads in processor

Abstract

A device comprises a first reservation station and a second reservation station. The first reservation station sends a first load micro instruction. If the first load micro instruction is a specified load micro instruction which indicates that operand is obtained from specified resources and is not from a cache in the core, the first reservation station carries out detection and instruction in a reservation bus. The second reservation station is coupled to the reservation bus, and sends new micro instructions depending on the first load micro instruction after a first number of clock periods. When that the first load micro instruction is the specified load micro instruction is indicated on the reservation bus, the second reservation station is used for caching the sending of the new micro instructions until the first load micro instruction obtains the operand. The specified resources comprise a system memory which is coupled to an out-of-order processor through a memory bus. The specified load micro instruction is used for deciding a memory space combined with the write-in of the system memory.

Description

technical field [0001] The present invention generally relates to a technique in the field of microelectronics, and in particular to an energy-saving mechanism for improving re-execution loads in an out-of-order processor. Background technique [0002] Airframe device technology has advanced rapidly over the past forty years. Especially in the development of microprocessors, starting from 4-bit, single-instruction, 10-micron devices, with the advancement of semiconductor production technology, designers can design more and more complex devices in structure and density. In the 1980s and 1990s, so-called pipeline microprocessors and superscalars developed to contain millions of transistors on a single chip. Now, 20 years later, 64-bit, 32-nanometer devices are in mass production, with one billion transistors on a single chip and containing multiple microprocessor cores to process data. [0003] In addition to parallel application of instructions in today's multi-core process...

AI Technical Summary

Problems solved by technology

In addition, even though the performance loss caused by the need to re-execute dispatched new instructions according to the above-mentioned acceleration technology is not large, the current inventors have found that its impact on power usage is noteworthy. For a large number of instructions in the above-mentioned When the condition is executed, the instruction is almost always re-executed

In addition, the initial execution of these instructions is inherently wasteful of power, so such a situation is detrimental to battery life, thermal profile, and reliability

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