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Processor and method for accessing to memory

A processor and memory technology, applied in electrical digital data processing, instruments, input/output to record carriers, etc., can solve problems such as increased burden on DRAM controllers, increased access response time, and inefficient data access.

Active Publication Date: 2016-05-11
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, when the processor sends these read / write commands to the DRAM controller, it usually does not perform DRAM-aware protocol scheduling (DRAM-aware protocol scheduling) on ​​the processor side for these read / write commands. Therefore, it will increase the burden on the back-end DRAM controller, and it will be less efficient in data access and increase the access response time

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  • Processor and method for accessing to memory
  • Processor and method for accessing to memory
  • Processor and method for accessing to memory

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Embodiment Construction

[0028] Certain terms are used in the specification and subsequent claims to refer to particular components. It should be understood by those skilled in the art that hardware manufacturers may refer to the same component by different terms. This specification and subsequent patent applications do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect electrical connection means, therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the The second device, or indirectly electrically connected to the second device through other devices or connection me...

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Abstract

The invention relates to a processor and a method for accessing to a memory. The processor comprises multiple storage modules and an arbiter; the multiple storage modules are respectively used for storing multiple read / write instructions; the multiple read / write instructions are used for demanding reading / writing the memory located out of the processor; the arbiter is coupled to the multiple storage modules and is used for receiving the multiple read / write instructions coming from the multiple storage modules and arranging the sequence for transmitting the multiple read / write instructions to a memory controller.

Description

technical field [0001] The present invention relates to a processor, especially a method for the processor to access an external memory. Background technique [0002] When the processor is performing operations, there will be multiple circuit modules inside that need to read data from the Dynamic Random-Access Memory (Dynamic Random-Access Memory, DRAM) or write data into the DRAM. Therefore, these circuit modules will A plurality of read / write commands are respectively sent to a DRAM controller to request a read / write DRAM operation. [0003] However, when the processor sends these read / write commands to the DRAM controller, it usually does not perform DRAM-aware protocol scheduling (DRAM-aware protocol scheduling) on ​​the processor side for these read / write commands. Therefore, the burden on the back-end DRAM controller will be increased, and the data access will be less efficient and increase the access response time. Contents of the invention [0004] Therefore, one...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/18G06F3/06
Inventor 赖奇劭张雅闵
Owner REALTEK SEMICON CORP