A Method of Improving Anti-Single Event Turnover Ability of Chip by Logic Design

Abstract

The invention discloses a method for improving single event upset resistance of chips through logic design. According to the method, logic design measures such as redundancy encoding and the like are adopted for the configuration registers, finite-state machines, data registers and memorizers of the chips, so that the single vent upset resistance of the chips can be greatly improved; and 3 interrupt signals are sent to the master control CPU of a system, so that the system is capable of grasping the single event upset conditions in the chips. At the cost of relatively low design complexity and relatively short design time, the method is capable greatly improving the reliability and adaptability of the chips under spatial single event environment, and reducing the probability of function error or function interruption caused by single event upset.

Description

technical field [0001] The invention relates to a method for improving the anti-single event flipping ability of a chip through logic design, in particular to a logic design method for improving the anti-single event flipping ability of a digital integrated circuit chip used in a space radiation environment. Background technique [0002] Unlike integrated circuit devices used in ground equipment, integrated circuit chips used in space vehicles may be incident by a single high-energy particle in space, generating high-density electron-hole pairs inside the chip, which are collected by reverse-biased PN junctions. As a result, the logic state inside the device may be flipped, that is, a single event flip occurs. Single-event flipping can cause device function errors or even function interruptions, which will affect system functions. Therefore, it is one of the effects that must be paid attention to in integrated circuit devices for aerospace applications. [0003] With the co...

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is: to overcome the disadvantages of difficulty and long cycle in realizing single-particle flip reinforcement design at the level of process design, and through a set of design methods irrelevant to process in the logic design stage, with a short design time and a very low The difficulty of design, realizing the single event flip hardening of the configuration register, finite state machine, data register, and memory respectively, can greatly improve the reliability and fault tolerance of the chip in the space single event environment, reaching or even exceeding the process design hardening Anti-single event upset performance; at the same time, through flexible and variable redundant coding, finite state machine hot backup redundant state, influence domain division, data clamping and other design methods, it overcomes the area power consumption of the traditional three-mode redundant reinforcement method Large and three-mode have low fault tolerance for input-level flipping and cannot protect memory, etc., to achieve chip-level or even system-level anti-single event flipping performance improvement

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