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Repairing method of retention time violation

A technology of hold time and repair method, applied in special data processing applications, instruments, electrical digital data processing and other directions, can solve problems such as hold time violation, space insertion buffer unit, and complete hold time violation repair, so as to reduce the impact, Eliminate the effect of overlapping cells

Active Publication Date: 2016-07-20
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0005] In high-density physical design, the existing timing repair tools cannot find enough space to insert buffer units on the basis of high-density design, and cannot completely repair the hold time violation. The present invention proposes a hold time violation repair method, which completely repairs all hold time violations by moving the position of existing cells and inserting suitable repair cells

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  • Repairing method of retention time violation
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  • Repairing method of retention time violation

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Embodiment Construction

[0054] Such as image 3 As shown, it is a flowchart of a method for repairing a hold time violation of the present invention, and the present invention includes the following steps:

[0055] The first step is to obtain the start point, end point and violation value of the path with hold time violation from the results of static timing analysis;

[0056] 1.1 Perform static timing analysis on the results of chip physical design, and obtain path reports of hold time violations in each scenario;

[0057] 1.2 Obtain the end point of the timing violation path, the signal transition time on the interconnection line of the input terminal of the terminal unit, the load of the interconnection line of the terminal unit and the violation value from the path report;

[0058] 1.3 Merge the paths with the same end points in each scenario, and the combined timing violation value is the maximum violation value in all scenarios, which is recorded as t i , to cover hold violations for all scen...

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Abstract

The invention relates to a repairing method of retention time violation.The method includes: acquiring the starting point, ending point and violation value of a path with the retention time violation from the result of static time sequence analysis; secondly, selecting the ending point of the path with the retention time violation as the to-be-inserted node of a repairing unit, and inserting one buffer unit or delay unit at the to-be-inserted node during each repairing so as to reduce the influence of the repairing unit insertion on the time sequence of other paths; thirdly, search the physical position for unit placing near the node with the inserted repairing unit, releasing the space required by the repairing unit through the position of the original unit in mobile design, and setting a target function to allow the total cost of the mobile unit to be the lowest so as to achieve low disturbance to the original design; fourthly, generating corresponding repairing logic, placing units and the engineering change order of mobile unit positions; fifthly, rewiring the connection relation with the logic being modified, extracting parasitic parameters, and performing static time sequence analysis to guarantee that the retention time is repaired completely.

Description

technical field [0001] The present invention relates to a method for repairing hold time violations in high density physical designs. Background technique [0002] With the continuous use of large-scale and ultra-large-scale integrated circuits, the size of the process has been continuously reduced, and the mainstream process has reached 40nm, and it is constantly developing to a smaller and more advanced process. At present, the most advanced process size under research in the world is the process of Intel Corporation, which has entered the order of tens of nanometers. The speed at which smaller and smaller process sizes replace existing processes is constantly accelerating, which requires physical design engineers to continuously shorten the production cycle in order to have a place in the fierce competition, especially for the start-up of my country's integrated circuit industry. Relatively late, the current situation of weak technology, the country has introduced relevan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 刘祥远陈跃跃刘必慰李振涛陈书明郭阳李寿萍胡春媚梁斌池雅庆陈建军
Owner NAT UNIV OF DEFENSE TECH
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