Chip Reliability Test Board and Its Test System

Abstract

The invention discloses a chip reliability test board and a test system thereof. Chip reliability test boards are used to carry multiple chips. The chips are arranged on the test board according to an array arrangement to form a plurality of chip rows and a plurality of chip columns. The chip reliability test board includes multiple output data lines and multiple input data lines. A plurality of output data lines are respectively coupled to data output pins of chips on the chip columns. A plurality of input data lines are respectively coupled to data input pins of chips on the chip column. The output data lines are respectively connected to a plurality of data receiving terminals of the reliability testing machine, and the input data lines are respectively connected to a plurality of first clock pulse signal terminals of the reliability testing machine.

Description

Technical field [0001] The invention relates to a test board and a test system, and in particular to a test board and a test system for chip reliability. Background technique [0002] With the evolution of electronic technology, electronic products have become important tools in people's lives today. Through the construction of integrated circuits, the volume of electronic products can be greatly reduced, which is more conducive to the applications in people's lives. [0003] To ensure the life cycle of the chip, the reliability test for the chip is an important and indispensable step in the design and production process of the chip. In the prior art, taking the reliability test machine F25 of flash memory chips applied to the serial interface as an example, the test machine F25 cannot be designed as a separate and independent simultaneous for the I / O pins with input / output. The function of the operation. In order to complete the reliability test of the chip with input / output pi...

AI Technical Summary

Problems solved by technology

In the prior art, taking the reliability test machine F25 of the flash memory chip applied to the serial interface as an example, the test machine F25 cannot be designed as a separate independent simultaneous Operation function

In order to complete the reliability testing of chips with input / output pins, complex testing procedures are often required to complete, resulting in difficulties in chip reliability testing.

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