Performance can be precisely controlled by multi-core multi-threaded processors

Abstract

A performance can precisely control multi-core multi-threaded processors, including OS-level configuration and monitoring interface, performance recording register set, hardware-level supervision thread processing core, resource recording register set, thread context register, central control unit and shared processor hardware Beneficial effects of the present invention: (1) N performance record register groups, N resource record register groups, and 1 hardware-level supervisory thread processing core are all new architectures, microarchitectures, and operating systems of multi-core multi-thread processors. The design of the mechanism realizes explicit regulation and precise control of multi-thread performance and resource allocation. (2) The OS-level configuration and monitoring interface of HLST reserves an interface for system collaborative design, effectively overcoming the problem of "emphasis on the overall, light on the individual" on the hardware and the "black box" of OS-level scheduling that are ubiquitous on general multi-core multi-threaded processors. box" effect.

Description

technical field [0001] The invention relates to a multi-core multi-threading (multi-core multi-threading) processor technology, in particular to a multi-core multi-threading processor technology whose performance can be precisely controlled. The invention belongs to the field of computer system design, and is used for explicit regulation of hardware resources of multi-core and multi-thread computer systems, especially multi-core and multi-thread processors, and precise control of thread performance. The specific application field is the multi-core multi-thread computer system, especially the multi-core multi-thread computer system structure design with high requirements on thread performance, real-time performance and determinism, including the design and implementation of OS-level resource allocation and thread performance control functions. . Background technique [0002] Computer systems have entered the era of on-chip multithreading (CMT) architecture, that is, the era ...

AI Technical Summary

Problems solved by technology

[0005] (2) The "black box" effect of OS-level scheduling: The OS's performance management of multithreading stops at scheduling selected threads or thread combinations to run on processors. It is difficult to monitor and manage the actual running status of the thread on-chip

[0006] (3) Lack of system-level comprehensive design: lack of system-level monitoring and control mechanisms and methods for the performance and resource allocation of multiple threads running simultaneously on multi-core multi-thread processors, and lack of related system-level collaborative design

[0007] In summary, although multi-core and multi-threading have greatly improved computing performance, there is still a lack of methods, designs, and implementations for precise control of multi-threading performance and resource occupation.

Images