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Method and device for starting basic input/output system (BIOS)

A consistent, node-based technology, applied in the computer field, can solve problems such as low compatibility of PCIE devices, reduced space, and reduced available memory address space

Active Publication Date: 2016-08-17
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, with the increase in the number of central processing units (Central Processing Units, referred to as CPUs) included in large-scale CC-NUMA systems, the MMCFG space occupied by each CPU is fixed, and the MMCFG space below 4GB increases accordingly. The address capacity of the following locations is fixed and limited. On the one hand, the Memory Mapped Input / Output (MMIO) space is reduced accordingly, and the less MMIO space limits the bus and interface standards (Peripheral Component Interface Express, PCIE for short). The number and functions of the devices cause the PCIE device compatibility of large-scale CC-NUMA system products to be low
On the other hand, the address space of the available memory below 4GB is reduced accordingly, and too low available memory may cause compatibility problems that the operating system cannot start

Method used

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  • Method and device for starting basic input/output system (BIOS)
  • Method and device for starting basic input/output system (BIOS)
  • Method and device for starting basic input/output system (BIOS)

Examples

Experimental program
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Embodiment 1

[0159] see Figure 4 , a BIOS startup method in the embodiment of the present invention is executed by the node, including:

[0160] S401. Enter the first access mode. In the first access mode, the maximum address accessed by the node is the first address; in the first access mode, perform the following steps from S402 to S407;

[0161] In this embodiment, "access mode" refers to a way for a processor (CPU) to address through a bus with a certain number of bits. For example, in the prior art, addressing is usually performed through a 32-bit or 64-bit bus. In this embodiment, the maximum space that can be addressed by the first access mode is smaller than the maximum space that can be addressed by the second access mode to be introduced later. For example, in this embodiment, the first access mode is a 32-bit access mode, that is, addressing is performed through a 32-bit bus, and the maximum addressing space (that is, the "first address" in step S401) is 4GB. Correspondingly, ...

Embodiment 2

[0202] Based on the foregoing embodiments, this embodiment specifically describes step S402 in the first embodiment.

[0203] Exemplary, such as Figure 5 As shown in the example, this node includes 4 CPUs, which are recorded as CPU0, CPU1, CPU2, and CPU3 respectively, and a local MMCFG space of 64 kilobytes (KB) is allocated for each CPU. The allocation results are as follows: CPU0 allocation 2G~2G+64M MMCFG space; CPU1 allocates 2G+64M~2G+64M+64M MMCFG space; and so on for the rest.

[0204] In this way, the local MMCFG spaces of the four CPUs are continuous, and when CPU0 accesses the address of 2G+64M, it will access the MMCFG space of CPU1, and then the Control and Status Register (CSR) register of CPU1 can be operated. When CPU1 accesses the address of 2G, it will access the MMCFG space of CPU0 and operate the CSR register of CPU0. The rest and so on. Realize that any CPU of this node can access the CSR registers of other CPUs in the node.

[0205] Specifically, allo...

Embodiment 3

[0222] Based on the foregoing embodiments, this embodiment specifically describes step S404 in the foregoing embodiments.

[0223] Exemplarily, the node can allocate the address of the MMCFG space in the global access address by configuring the DRAM Rule register, and can configure the INTERLEAVE_LIST register to set the address of the MMCFG space allocated through the DRAM Rule register in the global access address to the node's MMCFG space.

[0224] Among them, the DRAM Rule register is used for address allocation from the 0MB address to the maximum addressable space of the memory.

[0225] Specifically, by setting the Limit field of the DRAM_RULE_0-19 register to specify the upper limit address of the space, the attr field specifies whether the space is used for DRAM or MMCFG space, and the RULE_ENABLE field specifies whether the rule effectively allocates the memory space of the CPU in the node.

[0226] Exemplarily, the large-scale CC-NUMA system is a 32-way system, the ...

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Abstract

The embodiment of the invention provides a method and device for starting a basic input / output system (BIOS) and relates to the field of computers. On the premise of large-scale number extension of central processing units (CPUs) contained by a cache coherent non-uniform memory access (CC-NUMA) system, the BIOS starting does not affect occupation capacity of a memory-mapped I / O (MMIO) space and an available memory space below a first address of a global access address of the system. According to the concrete scheme, by distribution of local MMCFGs in a space of a node below a first address of a local access address of the node in a first access mode, memory initialization is performed; when memory unified addressing of the system is performed, the positions of addresses of MMCFG spaces of the node in the global access address of the system are moved, and are moved from the space below the first address to a space which is above the first address and can be accessed in a second access mode. The method and the device are used for BIOS starting.

Description

technical field [0001] The present invention relates to the field of computers, in particular to a method and device for starting a Basic Input / Output System (BIOS for short). Background technique [0002] With the development of science and technology, more and more high-performance servers are used in scientific research and business operations. Among them, the x86 large-scale Cache Coherence Non-Uniform Memory Access (CC-NUMA) system has been widely used due to its high performance, high scalability and easy programming environment. [0003] A large-scale CC-NUMA system generally consists of multiple individual server motherboards (node ​​boards) interconnected through the Cache Coherence interconnection network to form a large server running only one operating system. In general, large-scale x86 CC-NUMA multi-channel systems usually start their respective BIOSes based on 2-channel or 4-channel node boards. At a certain stage of the BIOS process, each node is included i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/44
CPCG06F9/44505G06F9/445G06F15/177G06F9/4411G06F9/4403G06F9/4405G06F9/44G06F12/023G06F2212/1044
Inventor 干耶卒仇连根李羿
Owner HUAWEI TECH CO LTD
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