41 results about "Memory-mapped I/O" patented technology

A method, computer program product, and distributed data processing system that allows a single physical I / O adapter, such as a PCI, PCI-X, or PCI-E adapter, to use a PCI adapter identifier to associate its resources to a system image and isolate them from other system images thereby providing I / O virtualization is provided. Specifically, the present invention is directed to a mechanism for sharing among multiple system images a conventional PCI (Peripheral Component Interconnect) I / O adapters, PCI-X I / O adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for communications. A mechanism is provided that allows a single physical I / O adapter, such as a PCI, PCI-X, or PCI-E adapter, to use a PCI adapter identifier to associate its resources to a system image and isolate them from other system images, thereby providing I / O virtualization.

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input / output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I / O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I / O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

A method, computer program product, and distributed data processing system that allows a single physical I / O adapter to validate that a memory mapped I / O address referenced by an incoming I / O operation is associated with a virtual host that initiated the incoming memory mapped I / O operation is provided. Specifically, the present invention is directed to a mechanism for sharing a PCI family I / O adapter and, in general, any I / O adapter that uses a memory mapped I / O interface for communications. A mechanism is provided that allows a single physical I / O adapter to validate that a memory mapped I / O address referenced by an incoming memory mapped I / O operation used to initiate an I / O transaction is associated with a virtual host that initiated the incoming memory mapped I / O operation.

A method, computer program product, and distributed data processing system for modifying one or more virtual resources that reside within a physical adapter, such as a peripheral component interconnect (PCI), PCI-X, or PCI-E adapter, and that are associated with a virtual host is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I / O adapters, PCI-X I / O Adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for host to adapter communications. A mechanism is provided for directly modifying one or more virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and that are associated with a virtual host.

A method, computer program product, and distributed data processing system for directly sharing an I / O adapter that directly supports adapter virtualization and does not require an LPAR manager or other intermediary to be invoked on every I / O transaction is provided. The present invention also provides a method, computer program product, and distributed data processing system for directly creating and initializing a virtual adapter and associated resources on a physical adapter, such as a PCI, PCI-X, or PCI-E adapter. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I / O adapters, PCI-X I / O adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for communications. A mechanism is provided for directly creating and initializing a virtual adapter and associated resources within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter. Additionally, each virtual adapter has an associated set of host side resources, such as memory addresses and interrupt levels, and adapter side resources, such as adapter memory addresses and processing queues, and each virtual adapter is isolated from accessing the host side resources and adapter resources that belong to another virtual or physical adapter.

A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I / O adapters, PCI-X I / O Adapters, PCI-Express I / O Adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for communications.

A method, computer program product, and distributed data processing system for directly sharing a network stack offload I / O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I / O transaction is provided. The present invention also provides a method, computer program product, and distributed data processing system for directly creating and initializing one or more virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I / O adapters, PCI-X I / O adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for host to adapter communications. A mechanism is provided for directly creating and initializing one or more virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and that are associated with a virtual host.

A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.

A method, computer program product, and distributed data processing system for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional Peripheral Component Interconnect (PCI) I / O adapters, PCI-X I / O adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for host to adapter communications.

A method, computer program product, and distributed data processing system that allows a single physical I / O adapter, such as a PCI, PCI-X, or PCI-E adapter, to associate its resources to a system image and isolate them from other system images, thereby providing I / O virtualization is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I / O adapters, PCI-X I / O adapters, PCI-Express I / O adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for communications. A mechanism is provided that allows a single physical I / O adapter, such as a PCI, PCI-X, or PCI-E adapter, to associate its resources to a system image and isolate them from other system images thereby providing I / O virtualization.

A method, computer program product, and distributed data processing system that allows a single physical I / O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I / O transaction that was initiated through a memory mapped I / O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I / O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I / O adapters, PCI-X I / O Adapters, PCI-Express I / O Adapters, and, in general, any I / O adapter that uses a memory mapped I / O interface for communications. A single physical I / O adapter validates that one or more direct memory access addresses referenced by an incoming I / O transaction initiated through a memory mapped I / O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I / O operation.

A mechanism for simultaneous multiple host access to shared centralized memory space via a virtualization protocol utilizing a network transport. The invention combines local memory interfacing with the handling of multiple hosts implementing virtualized memory-mapped I / O systems, such that the memory becomes a global resource. The end result is a widely distributed memory-mapped computer cluster, sharing a 2̂64 byte memory space.

The invention provides an RDMA (Remote Direct Memory Access) communication method between non-tightly-coupled systems of a sharing system address space. A destination node is remotely accessed by a source node through a direct memory access instruction and a remote direct memory access RDMA connection is established between the source node and the destination node; data transmission is executed between the source node and the destination node after the RDMA connection is established; the RDMA connection is released after the data transmission is achieved, wherein shared memory resources and I / O resources of the remote destination node are mapped into a local MMIO (Memory-Mapped I / O) address space of the source node. According to the RDMA communication method between the non-tightly-coupled systems of the sharing system address space, the rapid stable data transmission between non-tightly-coupled nodes can be implemented.

A component, system and method for simulation of a PCI device's memory-mapped I / O register(s) are provided. The PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I / O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system. The memory-mapped I / O space simulator simulates behavior of a simulated PCI device and can comprise can comprise a thread that monitors the simulated memory-mapped I / O registers for a change in order to simulate behavior of the simulated PCI device. Additionally and / or alternatively, the memory-mapped I / O space simulator can comprise a thread that changes at least one of the simulated memory mapped I / O registers in order to simulate behavior of the simulated PCI device.

A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I / O register of the model is mapped into memory-mapped I / O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I / O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

An apparatus and method for outbound I / O write-combining are described. In one embodiment the method includes the detection of a write transaction request directed to an I / O device. Once detected, it is determined whether an address associated with the detected write transaction falls within a predetermined write-combinable range of the memory mapped I / O space assigned to the I / O device. When the transaction address falls within a write-combinable range, data associated with the detected write transaction is stored within a buffer corresponding to the transaction address. Accordingly, one embodiment of the present invention provides write-combining for data written to an I / O port associated with a memory mapped I / O address space.

A mechanism for detecting, associating, establishing, and executing an optimal virtualization protocol between a host and a given virtualized device. An Intelligent Host Bus Adapter (IHBA) is claimed that combines storage virtualization with I / O system resource virtualization and incorporates both Dynamic Storage Configuration Protocol (DSCP) and Dynamic I / O Configuration Protocol (DICP) on a common CPU offload platform. The invention enables a comprehensive virtualization solution that includes automatic detection and selection of optimal storage virtualization as well as memory-mapped I / O virtualization protocols on a per resource basis.

The embodiment of the invention provides a method and device for starting a basic input / output system (BIOS) and relates to the field of computers. On the premise of large-scale number extension of central processing units (CPUs) contained by a cache coherent non-uniform memory access (CC-NUMA) system, the BIOS starting does not affect occupation capacity of a memory-mapped I / O (MMIO) space and an available memory space below a first address of a global access address of the system. According to the concrete scheme, by distribution of local MMCFGs in a space of a node below a first address of a local access address of the node in a first access mode, memory initialization is performed; when memory unified addressing of the system is performed, the positions of addresses of MMCFG spaces of the node in the global access address of the system are moved, and are moved from the space below the first address to a space which is above the first address and can be accessed in a second access mode. The method and the device are used for BIOS starting.

A mechanism and method for redefining an application specific integrated circuit's I / O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I / O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I / O bus ownership when it is available. Once ownership is granted, I / O bus pins are defined and access is granted.

An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss. The data cache has pipeline stages that parallel portions of the main microprocessor pipeline. Replay buffers are employed to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache pipeline stages are restored upon detection that the stall will terminate. The bus requests for the missing data are issued only if the stalled instruction does not access a memory-mapped I / O region of the memory address space.

To improve upon some of the characteristics of current storage systems in general and block data storage systems in particular, exemplary embodiments combine state-of-the art networking techniques with state-of-the-art data storage elements in a novel way. To accomplish this combination in a highly effective way, it is proposed to combine networking remote direct memory access (RDMA) technique and storage-oriented memory mapped input output (MMIO) technique in a system to provide direct access from a remote storage client to a remote storage system with little to no central processing unit (CPU) intervention of the remote storage server. In some embodiments, this technique may reduce the required CPU intervention on the client side. These reductions of CPU intervention potentially reduce latency while providing performance improvements, and / or providing more data transfer bandwidth and / or throughput and / or more operations per second compared to other systems with equivalent hardware.