A Method of Using Compiler to Automatically Generate Width-Configurable Bus Layout

An automatic generation and compiler technology, applied in the direction of instruments, special data processing applications, calculations, etc., can solve the problems of time-consuming and labor-intensive, lack of flexibility and configurability, etc., to improve flexibility, save manpower and time, and reduce duplication. design effect

Active Publication Date: 2019-01-25
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional bus layout is manually designed by engineers, which is time-consuming and labor-intensive
And when multiple buses with different bit widths are required, multiple bus layouts need to be redesigned, which lacks flexibility and configurability

Method used

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  • A Method of Using Compiler to Automatically Generate Width-Configurable Bus Layout
  • A Method of Using Compiler to Automatically Generate Width-Configurable Bus Layout
  • A Method of Using Compiler to Automatically Generate Width-Configurable Bus Layout

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Embodiment Construction

[0022] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0023] The present invention uses a compiler to automatically generate a method for a bus layout with configurable bit width, such as figure 2 As shown, it specifically includes the following steps.

[0024] The first step is to design the layout of the basic unit of the bus by the engineer, and add information recognizable to the compiler such as the boundary of the layout unit, the name of the via, and the coordinates of the via to the layout; the engineer provides the bus bit width n that the compiler needs to generate; Among them such as image 3 As shown, the marking information of the basic unit layout of the bus includes the via name and coordinates via_name(via_x, via_y); it includes the horizontal metal pattern Metal_H, the vertical metal pattern Metal_V, the name of the vi...

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PUM

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Abstract

The invention provides a method for automatically generating a bit width configurable bus layout by a compiler. The method is characterized in that working efficiency is high; configuration is flexible; the compiler successively carries out horizontal and longitudinal splicing of bus basic unit layouts according to set bus bit widths, and then a horizontal metal transmission line and a bus metal transmission line are connected correspondingly through punching; the length and the width of each bus basic unit layout are marked as X and Y respectively, the bus basic unit layout comprises multiple horizontal metal graphs Metal_H which are arranged in a mutually perpendicular manner as well as the same quantity of longitudinal metal graphs Metal_V, and the quantity of the horizontal metal graphs Metal_H and the longitudinal metal graphs Metal_V is equal to the quantity of signals contained by each bit width; intersection positions between the horizontal metal graphs Metal_H and the longitudinal metal graphs Metal_V which represent the same signals are corresponding positions of through holes; and names and coordinates of the through holes which can be identified by the compiler as well as unit boundary information are marked on the bus basic unit layouts.

Description

technical field [0001] The invention relates to the field of integrated circuit layout generation, in particular to a method for automatically generating a bus layout with configurable bit width by using a compiler. Background technique [0002] In the field of integrated circuit layout, the bus is a public communication trunk that connects various layout modules to transmit information, and it is composed of multiple metal transmission lines. like figure 1 As shown, it is an example of a bus with a bit width of n connecting two modules. Module A has port DA <n-1:0>, module B has port DB <n-1:0>. Bus BUS <n-1:0>Lateral connection port DA <n-1:0>and port DB <n-1:0>, longitudinally connected to the BUS through punched leads <n-1:0>. The traditional bus layout is manually designed by engineers, which is time-consuming and labor-intensive. And when multiple buses with different bit widths are required, multiple bus layouts need to be...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 熊保玉拜福君
Owner XI AN UNIIC SEMICON CO LTD
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