An evaluation method of a chip power consumption evaluation platform

Abstract

The invention provides an assessment method for a chip power consumption assessment platform. The method comprises the steps of compiling c program codes prepared to run in a test by a CPU to generate an assembly program; adding a log printing instruction to each instruction involving an address operation; performing rtl simulation on rtl design to generate an address operation log file; reading the address operation log file and address interval information of all accessible modules, and summarizing addresses subjected to the address operation; reading netlist designs of the modules and svf files corresponding to the modules by a netlist mapping analysis unit, analyzing a mapping relationship of each logic node, mapping wavy nodes of rtl into nodes of netlists, calculating logic values of standard_cell units added in the netlists, and mapping rtl simulation waveforms into netlist waveforms; and finally performing power consumption analysis to obtain power consumption data of a specified module. Therefore, the chip simulation speed is greatly increased.

Description

technical field [0001] The invention relates to a SOC chip simulation technology, in particular to an evaluation method of a chip power consumption evaluation platform. Background technique [0002] With the rapid increase of SOC chip scale, the simulation workload for SOC verification also increases rapidly. Especially in the netlist verification stage of the chip as a whole, since all simulation behaviors have added timing information, the server has a huge amount of computation. The simulation time of a verification stimulus often takes about a week to run, and the verification of a chip usually Hundreds of verification incentives are required. Due to the long time of verification simulation, it poses a great challenge to the development time of the entire chip. So how to reduce the simulation time of large-scale SOC is a very meaningful work, but there is no better way to solve this problem at present. Contents of the invention [0003] The technical problem to be so...

AI Technical Summary

Problems solved by technology

Especially in the netlist verification stage of the chip as a whole, since all simulation behaviors have added timing information, the server has a huge amount of computation. The simulation time of a verification stimulus often takes about a week to run, and the verification of a chip usually Hundreds of verification incentives are required. Due to the long time of verification simulation, it poses a great challenge to the development time of the entire chip

Therefore, how to reduce the simulation time of large-scale SOC is a very meaningful work, but there is currently no better way to solve this problem

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