A sram bit line leakage current effect suppression circuit
A technology for suppressing circuit and leakage current, applied in information storage, static memory, digital memory information and other directions, can solve problems such as increasing power consumption, affecting SA drive capability, voltage reduction, etc. The effect of stability
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[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0027] Embodiments of the present invention provide a novel SRAM bit line leakage current effect suppression circuit, such as figure 1 As shown, it is a schematic diagram of the structure after adding a suppression circuit to the traditional SRAM circuit structure. One end of the suppression circuit is respectively connected to the bit lines BL and BLB in the SRAM, and the other end is connected to the input signals sa_in and SA of SA. Take sa_in ...
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