A sram bit line leakage current effect suppression circuit

A technology for suppressing circuit and leakage current, applied in information storage, static memory, digital memory information and other directions, can solve problems such as increasing power consumption, affecting SA drive capability, voltage reduction, etc. The effect of stability

Active Publication Date: 2019-04-16
ANHUI UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this solution is not suitable for SRAM operating at high frequency, because the introduction of additional compensation current increases power consumption
Moreover, the voltage reaching the input terminal of SA is reduced, which affects the driving ability of SA

Method used

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  • A sram bit line leakage current effect suppression circuit
  • A sram bit line leakage current effect suppression circuit
  • A sram bit line leakage current effect suppression circuit

Examples

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Embodiment Construction

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0027] Embodiments of the present invention provide a novel SRAM bit line leakage current effect suppression circuit, such as figure 1 As shown, it is a schematic diagram of the structure after adding a suppression circuit to the traditional SRAM circuit structure. One end of the suppression circuit is respectively connected to the bit lines BL and BLB in the SRAM, and the other end is connected to the input signals sa_in and SA of SA. Take sa_in ...

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Abstract

The invention discloses a novel static random access memory (SRAM) bit line leak current effect suppression circuit. The circuit comprises two P-channel metal oxide semiconductor (PMOS) pipes P1 and P2 and two capacitors C1 and C2. One end of the capacitor C1 is connected to a bit line BL in the SRAM, the other end of the capacitor C1 is connected to a drain electrode of the PMOS pipe P1, the two ends of the capacitor C1 are connected to an input end sa_in of a sense amplifier in the SRAM, a grid electrode of the PMOS pipe P1 is connected to a control signal CON<->, a source of the PMOS pipe P1 is connected to a voltage drain drain (VDD), one end of the capacitor C2 is connected to a bit line BLB in the SRAM, the other end of the capacitor C2 is connected to a drain electrode of the PMOS pipe P2, the two ends of the capacitor C2 are connected to an input end sa_in <-> of the sense amplifier in the SRAM, a grid electrode of the PMOS pipe P2 is connected to the control signal CON<->, a source of the PMOS pipe P2 is connected to the VDD and a potential difference between the input ends sa_in and sa_in <-> of the sense amplifier replaces a potential difference between the bit lines BL and BLB. The suppression circuit can improve leakage current-caused influence on SRAM reading, improve reading stability and improve leakage current interference resistance of a device.

Description

technical field [0001] The invention relates to the field of integrated circuit (IC) design, in particular to a novel SRAM bit line leakage current effect suppression circuit. Background technique [0002] With the continuous development of semiconductor technology, Static Random Access Memory (SRAM) has been widely used in high-performance systems that require fast access, such as computers, portable mobile devices, automotive electronics, sensors and medical equipment. Improving the reliability of the chip, reducing the cost and power consumption of the chip, and improving system performance have all played a vital role. Therefore, in-depth and detailed research on SRAM has important theoretical value and practical application significance for the development of low-power high-performance memory with independent intellectual property rights in my country and the promotion of the development of microelectronics technology in China. [0003] However, with the continuous imp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/419
CPCG11C11/419
Inventor 张景波安祥文蔺智挺吴秀龙彭春雨黎轩陈军宁
Owner ANHUI UNIVERSITY
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