Multi-core processor inter-core communication method and device
A technology for multi-core processors and inter-core communication, applied in the field of inter-core communication methods and devices for multi-core processors, capable of solving the problems of CPU processing task capability and low resource utilization
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Embodiment 2
[0095] Such as Figure 7 As shown, it is a flowchart of an inter-core communication method for a multi-core processor provided in Embodiment 2 of the present invention, including:
[0096] S701: The sending core determines that a message needs to be sent to the receiving core.
[0097] In a specific implementation, the sending core stores the message to be sent in a certain memory unit of the computer operating system, and the sending process transmits the first address of the memory unit.
[0098] S702: Determine whether the timer of the corresponding sending core when the sending core communicates with the receiving core is turned on. If it is enabled, go to S703; otherwise, go to S704.
[0099] S703: Store the message to be sent in the first sending buffer queue of the sending core, and wait for the timer of the sending core to expire.
[0100] S704: Determine whether there are idle elements in the message receiving queue of the receiving core. If not, go to S705, and i...
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