Metallized through-hole structure and manufacturing method thereof

Abstract

The invention provides a metalized through hole structure and a manufacturing method thereof. The manufacturing method of the metalized through hole structure comprises the following steps: using an etching medium which can etch an epitaxial structure and cannot etch a compound semiconductor substrate to etch the epitaxial structure on the substrate from the upper surface of the epitaxial structure to form an epitaxial groove, and making the etching automatically stop on the substrate; forming a front metal layer on the epitaxial structure and on the inner surface of the epitaxial groove; using an etching medium which can etch the substrate and cannot etch the epitaxial structure or the front metal layer to etch the substrate from the lower surface of the substrate to form a substrate groove, and making the etching automatically stop on the epitaxial structure and the front metal layer or automatically stop on the front metal layer, wherein the bottom of the substrate groove and the bottom of the epitaxial groove at least partially contact; and forming a back metal layer under the substrate and on the inner surface of the substrate groove, and making the back metal layer contact the front metal layer. Therefore, the area of the front metal layer is reduced greatly, and the size of elements can be reduced greatly in application.

Description

technical field [0001] The invention relates to a metallized through-hole structure and a manufacturing method thereof. Background technique [0002] Figure 1A ~ Figure 1E A schematic cross-sectional view of making a metallized through-hole structure for the prior art. in Figure 1A , forming an etch stop layer 2 on a substrate 1 , then forming an epitaxial structure 3 on the etch stop layer 2 , and then forming a front metal layer 4 on the epitaxial structure 3 . At this time, the lower surface 7 of the substrate 1 faces downward. Please refer to Figure 1B ,Will Figure 1A The structure of the substrate 1 is turned over 180 degrees, so that the lower surface 7 of the substrate 1 that originally faces downward becomes upward. A groove 5 is etched out of the substrate 1 so that the etching stops at the etch stop layer 2 . At this time, the bottom of the lower groove 5 is the etching stop layer 2 . Please refer to Figure 1C , etching the etch stop layer 2 at the bot...

AI Technical Summary

Problems solved by technology

Figure 1F An example is the case where the source electrode length L1 is long, and the lower groove length L2 cannot be individually matched with the source electrode length L1 of the transistor to form an appropriate size, and sometimes it can only be cut into two or three

[0003] However, the prior art has the following disadvantages when making the metallized through-hole structure: Shortcoming 1, between the substrate 1 and the epitaxial structure 3, or in some cases in the epitaxial structure 3, often need special To make a layer of etch stop layer 2 to control the process of etching the lower groove 5

In addition to the steps of making this layer of etch stop layer 2, there are also relatively many steps of etching this layer of etch stop layer 2, thus increasing the cost of manufacturing and materials.

[0004] Disadvantage 2. Etching the lower groove 5 starts from the lower surface 7 of the substrate 1. It is necessary to align and position the lower surface 7 of the substrate 1 first and delineate the groove etching area to define the lower groove etching area. After that, the etch step can begin

If the lower groove 5 cannot be cleaned effectively, the quality of forming the back metal layer 6 will be seriously affected later.

On the other hand, if the source electrode width W1 is enlarged, the size of the transistor cannot be effectively reduced, and the number of transistors that can be laid out on the same wafer will be greatly reduced.

[0005] Disadvantage 3. The aspect ratio design of the lower groove 5 cannot be effectively reduced. In addition to increasing the difficulty of cleaning the lower groove 5, relatively, the efficiency of etching the lower groove 5 cannot be effectively improved.

[0006] Disadvantage 4. When many transistors of different sizes are laid out on the same wafer at the same time, the length L1 of the source electrode of some transistors is longer, and the length L1 of the source electrode of some transistors is shorter, resulting in a longer length L1 of the source electrode, and the length L2 of the lower groove needs to be Paired with a lower groove length L2 with a shorter source electrode length L1 to shorten

The disadvantage is that the length L2 of the lower groove cannot be designed individually with the length L1 of the source electrode of the transistor to form an appropriate size, and sometimes it can only be cut into two or three

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