A Bit Cycling Method for Improving the Dynamic Performance of Hybrid Resistor-Capacitor Analog-to-Digital Converters
A technology of analog-to-digital converters and mixed resistors, which is applied in the field of high-precision analog-to-digital converters, can solve the problems of interrupting the normal operation of analog-to-digital converters, increasing algorithm complexity, and difficulty in on-chip implementation, achieving the sacrifice of sampling rate and structure Simple, easy-to-achieve effects
Active Publication Date: 2019-08-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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The disadvantage of analog correction in the foreground is that an additional correction DAC needs to be introduced, and the normal operation of the analog-to-digital converter needs to be interrupted
Background digital calibration usually uses the "Least Mean Square Error" (LMS: Least MeanSquare) algorithm to correct the mismatch of capacitors, and the calibration scheme based on the LMS algorithm has high precision and good calibration effect under the given error modeling conditions. However, if the initial value is not selected properly, it will increase the complexity of the algorithm, and even cause problems such as non-convergence of the algorithm, which is not easy to implement on-chip
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[0022] The present invention proposes a bit cycle method that can improve the dynamic performance of successive approximation analog-to-digital converters, such as figure 2 As shown, will figure 1 The highest bit (MSB) capacitor 16C is split into 4C, 2C, C, C, 4C, 2C, C, and C, and the second highest bit (MSB-1) capacitor 8C is split into 4C, 2C, C, and C. figure 1 The total capacitance 32C of the medium and high 5-bit capacitor DAC is divided into four groups, and these four groups of capacitors are in figure 2 The first group of capacitors C13-C16 is represented by black, the second group of capacitors C9-C12 is represented by purple, the third group of capacitors C5-C8 is represented by red, and the fourth group of capacitors C1-C4 is represented by blue It means that each group contains 8 unit capacitors, namely 4C, 2C, C, and C. Each bit cycle uses a different combination of capacitors to achieve dynamic averaging of capacitance errors, thereby achieving the purpose of...
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The invention discloses a bit cycle method for improving the dynamic performance of a mixed resistance-capacitance analog-to-digital converter, and the technical field of application is a high-precision analog-to-digital converter in the field of microelectronics and solid-state electronics. The bit cycle method proposed by the present invention is applicable to successive approximation analog-to-digital converters of any structure. The sub-bit cycle changes the capacitor order to achieve the effect of dynamic averaging of the capacitor error. It is characterized in that it does not need to introduce any correction algorithm, does not need to introduce a correction DAC, does not sacrifice the sampling rate of the analog-to-digital converter, and does not interrupt the normal operation of the analog-to-digital converter. The bit cycle method proposed by the present invention can dynamically average the capacitance error, therefore, compared with the traditional correction method that relies on correction DAC and correction algorithm to improve linearity, it has simpler structure, smaller occupied chip area, and easier on-chip achieved effect.
Description
technical field [0001] The invention relates to a novel successive approximation analog-to-digital converter (SAR ADC) bit cycle method, and the technical field of direct application is a high-precision analog-to-digital converter in the field of microelectronics and solid-state electronics. Background technique [0002] The analog-to-digital converter converts the real-world analog signal into a digital signal. It is a process of filtering, sample-holding and encoding. The analog-to-digital converter has been widely used in various on-chip systems. The requirements of different systems are different, and the performance of the analog-to-digital converter has a great influence on the stability, reliability and durability of the system. [0003] The performance index of the analog-to-digital converter is usually explained from two aspects: static parameters and dynamic parameters. The static parameters mainly include offset (Offset), missing code (Missing Code), monotonicity ...
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IPC IPC(8): H03M1/46H03M1/40
CPCH03M1/40H03M1/46
Inventor 樊华阎波陈伟建刘兴泉
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA