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Power packaging module of multi-power chips and manufacturing method of power chip unit
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A technology of power chips and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor/solid-state device components, etc., can solve the problems of power module efficiency reduction and difficulty in realizing power chip spacing, and improve placement efficiency , spacing shortened, and the effect of reducing the maximum junction temperature
Active Publication Date: 2019-03-15
DELTA ELECTRONICS (SHANGHAI) CO LTD
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[0005] Aiming at the problems existing in the prior art, the present invention provides a multi-power chip power package module and a manufacturing method of the power chip unit, so as to solve the problem that the power chip spacing in the prior art is difficult to achieve a smaller spacing, which leads to the efficiency of the power module. Reduced technical issues
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Embodiment 1
[0074] This embodiment provides a power packaging module for multi-power chips, the structural diagram is as follows Figure 13 shown, including:
[0075] A power chip unit, including at least two power chips 131 arranged in parallel and a connector 132 connecting the two power chips 131;
[0076] A substrate 133, carrying a power chip unit, the substrate includes a metal layer (not shown in the figure), and the metal layer is electrically connected to the power chip unit;
[0077] The sealing layer 134 is used to seal the surface of the substrate 133 to isolate the power chip unit from the surrounding environment;
[0078] The materials of the connecting body 132 and the sealing layer 134 are different insulating materials, the space between the two power chips T1 and T2 arranged in parallel is less than or equal to the preset width, and the connecting body 132 is filled in the space to connect and insulate the two parallel power chips T1 and T2. Set the power chips T1 and ...
Embodiment 2
[0089] Based on the connection between the power chip and the metal layer through the metal bonding wire in the first embodiment above, this embodiment also provides a power packaging module with multiple power chips, in which two power chips in the power chip unit are connected in series, and parallel The set width of the connecting body in the chip interval is less than or equal to the preset width so as to reduce the parasitic inductance existing in the two serially connected power chips connected by the connecting body.
[0090] The schematic diagram of the structure of the serial chip package module realized by metal bonding wire is as follows: Figure 15 As shown, the two power chips are planar power chips, which can be attached to the substrate 151 (the substrate is an insulating material) through the connection material 154 provided at the bottom of the chip 153 as described in the first embodiment. Substrate (non-common substrate means that the substrates of multiple ...
Embodiment 3
[0093] Based on the connection between the power chip and the metal layer through the metal bonding wire in the first embodiment above, this embodiment also provides a multi-power chip power package module, in which two power chips in the power chip unit are connected in parallel, and the parallel connection The width of the connecting body in the chip interval is less than or equal to the preset width to improve the uniformity of the parasitic inductance existing in the two parallel-connected power chips connected by the connecting body.
[0094] The schematic diagram of the structure of the parallel chip package module realized by metal bonding wire is as follows: Figure 16 As shown, the two power chips can be mounted on the substrate 161 (the substrate is an insulating material) through the connection material 164 provided at the bottom of the chip 173 as described in Embodiment 1, and the chips are connected through the connecting body 166, and the chips It is a non-commo...
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Abstract
The invention discloses a power packaging module of a multi-power chip and a manufacturing method of a power chip unit. The power packaging module of a multi-power chip includes a power chip unit, including at least two power chips arranged in parallel and a connecting body connecting the two power chips; The substrate carries the power chip unit, the substrate includes a metal layer, and the metal layer is electrically connected to the power chip unit; the sealing layer isolates the power chip unit placed on the substrate from the surrounding environment, and realizes the sealing of the power chip unit; the connector and the sealing layer The materials of the layers are different insulating materials, the space between the two power chips arranged in parallel is less than or equal to the preset width, and the connector is filled in the space to connect and insulate the two power chips arranged in parallel. In the packaging process, multiple chips can be mounted at one time, which improves the mounting efficiency, and shortens the distance between power chips and reduces the parasitic inductance between power chips, which is conducive to reducing the maximum junction temperature of chips and improving the reliability of power packaging modules.
Description
technical field [0001] The invention relates to the technical field of power chip packaging, in particular to a power packaging module of multiple power chips and a method for manufacturing a power chip unit. Background technique [0002] There are many types of packages for semiconductor power modules, which are distinguished by sealing materials in industrial products. The two commonly used packages are Gel type and Molding type. Whether it is silicone filling or plastic packaging, the surface electrodes on the chip and the DBC (Direct Bonded Copper, direct copper-clad ceramic) circuit pattern are all connected to the internal electrical signals of the module through the lead (mostly aluminum wire) bonding process (Wire Bonding). [0003] The chip mounting process usually uses a chip mounter (Die Bonder) to pick up the chip from the cut wafer (Wafer), and mount the chip to the DBC substrate. In the die bonding process, from picking up the chip through the suction nozzle w...
Claims
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Application Information
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