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Shift register and driving method thereof, gate driving circuit, and display device

A shift register and driving signal technology, applied in static memory, digital memory information, instruments, etc., can solve problems such as potential leakage, abnormal display, signal changes of pull-down nodes, etc.

Inactive Publication Date: 2017-03-15
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the low potential maintenance stage, the potential of the gate of the pull-down transistor will leak, that is, the potential of the signal of the pull-down node will change, causing the pull-down transistor to not be fully turned on, and may even cause the pull-down transistor to be cut off, thereby causing the drive signal output terminal The situation that the low potential cannot be maintained reduces the stability of the shift register, which may cause abnormalities in the display

Method used

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  • Shift register and driving method thereof, gate driving circuit, and display device
  • Shift register and driving method thereof, gate driving circuit, and display device
  • Shift register and driving method thereof, gate driving circuit, and display device

Examples

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Embodiment 1

[0130] by Figure 3a The structure of the shift register shown is taken as an example to describe its working process, wherein, in Figure 3a In the shift register shown, all the switch transistors are N-type switch transistors, and each N-type switch transistor is turned on under the action of a high potential, and is turned off under the action of a low potential; the potential of the reference signal terminal VSS is a low potential, and the corresponding The input and output timing diagram is as follows Figure 4a Shown, specifically, select as Figure 4a There are five stages in the shown input-output timing diagram, the first stage T1 , the second stage T2 , the third stage T3 , the fourth stage T4 and the fifth stage T5 .

[0131] In the first phase T1, Input=1, Reset=0, CLK=0, CS=0.

[0132] Since Input=1, both the first switching transistor M1 and the third switching transistor M3 are turned on. Since the first switching transistor M1 is turned on to provide the si...

Embodiment 2

[0148] by Figure 3b The structure of the shift register shown is taken as an example to describe its working process, wherein, in Figure 3b In the shift register shown, all the switching transistors are P-type switching transistors, and each P-type switching transistor is turned on under the action of a low potential, and is turned off under the action of a high potential; the potential of the reference signal terminal VSS is a high potential, and the corresponding The input and output timing diagram is as follows Figure 4b Shown, specifically, select as Figure 4b There are five stages in the shown input-output timing diagram, the first stage T1 , the second stage T2 , the third stage T3 , the fourth stage T4 and the fifth stage T5 .

[0149] In the first phase T1, Input=0, Reset=1, CLK=1, CS=1.

[0150] Since Input=0, both the first switching transistor M1 and the third switching transistor M3 are turned on. Since the first switching transistor M1 is turned on to prov...

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Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register comprises an input module, a reset module, a node control module, a potential maintenance module, a first output module, and a second output module. Through cooperation of the six modules, the potential maintenance module can keep the potential of a second node to ensure normal output of the second output module, so that the output stability of the shift register is improved, and the output of the driving signal output end is more stable.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register, a driving method thereof, a gate driving circuit and a display device. Background technique [0002] With the rapid development of display technology, the display panel is more and more developed towards the direction of high integration and low cost. Among them, the gate driver on array (Gate Driver on Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) gate switching circuit on the array substrate of the display panel to form a scan drive for the display panel, so that the gate driver can be omitted. The wiring space of the Bonding area of ​​the integrated circuit (Integrated Circuit, IC) and the fan-out (Fan-out) area can not only reduce the product cost in terms of material cost and manufacturing process, but also enable the display panel to achieve Beautiful design with symmetry on both sides and narrow frame; moreover, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/20G11C19/28
CPCG09G3/20G09G2310/0286G11C19/28G09G3/3266G09G3/3674G09G3/2092G09G2310/0267G09G2310/08
Inventor 王洪军
Owner BOE TECH GRP CO LTD
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