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A low-complexity AES integrated encryption and decryption implementation method

A low-complexity, encryption-decryption technology, applied in the field of low-complexity AES integrated encryption and decryption, can solve the problems of high and low complexity in the implementation of AES encryption and decryption

Inactive Publication Date: 2020-11-03
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] The purpose of the present invention is to provide a low-complexity implementation of an AES integrated encryption and decryption device based on FPGA (hereinafter referred to as the encryption and decryption device), so as to solve the problem that the complexity of the AES encryption and decryption device in the prior art is too high. question

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  • A low-complexity AES integrated encryption and decryption implementation method
  • A low-complexity AES integrated encryption and decryption implementation method
  • A low-complexity AES integrated encryption and decryption implementation method

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Embodiment Construction

[0040] Combine below Figure 10 , figure 1 and figure 2 Describe the process of row conversion operation performed by the row conversion module provided by the present invention. First, describe the process of row shift operation. At this time, the strobe signal MODE of the row conversion module is set to 0, and the data selector selection register 23 outputs.

[0041] When the row transformation module provided by the present invention is used to perform the row displacement operation, the data is sequentially input into the row transformation module in byte order, and when the first data S0 is input, the counter 20 starts counting from 0, and at this moment, the register 22 is 0, and the register 23 is 0, therefore, the output of shifter 26 is 0, and the output of adder 21 is 0, that is, S0 is written to address 0, figure 1 The order of S0 has not changed; when the second data S1 is input, the counter 20 becomes 1, and the register 22 is 1, and the register 23 is 3. There...

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Abstract

The invention provides a design architecture and an implementation mode of an FPGA-based AES integrated encryption and decryption device having low complexity. Due to optimal design of a row transformation unit, a column transformation unit, a box transformation unit and a data caching unit in the encryption and decryption device, the architecture of an encryption device and the architecture of a decryption device are highly reusable; therefore, the resource consumption is reduced; the complexity is reduced; and the operation speed is increased.

Description

technical field [0001] The invention belongs to the communication field, and in particular relates to a method for realizing a low-complexity AES integrated encryption and decryption device. Background technique [0002] With the advancement of science and technology, the exchange of information has become more frequent in people's lives, and ensuring the safe transmission of information has become a vital part of communication. The National Institute of Standards and Technology (NIST) formulated and published the AES (Advanced Encryption Standard) encryption algorithm in 2001, which has replaced the DES encryption algorithm to become one of the most popular encryption methods today. The AES encryption algorithm has the characteristics of high security, simple process, and compact encoding, which can meet the needs of information encryption in most cases. [0003] AES is an encryption algorithm for symmetric key blocks. To meet the needs of different scenarios, the AES enc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/06
CPCH04L9/0631
Inventor 赵岭胡杨王天娇李勣
Owner BEIHANG UNIV