A device and method for dynamic multipath delay simulation based on synchronous random access memory

Abstract

The present invention discloses that the present invention proposes a dynamic multipath time delay simulation device and method based on synchronous random access memory. The device adopts dislocation address control technology, and realizes a large-scale multipath time delay simulation based on synchronous random access memory, which can Simulate the group delay of up to 4 reflection clusters; based on polyphase filtering technology, it can achieve high-precision time delay simulation with an accuracy of 0.1ns without increasing the sampling rate; at the same time, it adopts linear function control technology and nonlinear high-precision Fitting technology realizes linear and nonlinear multipath dynamic time delay simulation of up to 24 paths inside FPGA. The device has the advantages of flexible configuration, simple structure and the like.

Description

technical field [0001] The invention relates to a dynamic multipath delay simulation device and method based on a synchronous random access memory. Background technique [0002] With the rapid development of science and technology, people have higher and higher requirements for the reliability and real-time performance of wireless communication. The channel simulator can simulate the influence of actual communication scenarios on wireless signal propagation in the laboratory, and is widely used in the research and development and testing of communication equipment. In the process of wireless signal transmission, affected by surrounding scatterers, the signal arriving at the receiving end is formed by the superposition of many reflection paths, and there is a relative time delay between the signals of many reflection paths, especially for satellite channels and aviation channels. More than 10ms; at the same time, in order to ensure the accuracy of the simulation, the delay a...

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Problems solved by technology

[0003] In the existing channel simulation technology, the internal storage unit of FPGA is usually used to realize the multipath delay simulation. This method is limited by the internal storage resources of the FPGA and cannot realize a wide range of multipath delay simulation. Moreover, this method is limited by its own system clock. Restrictions, taking the 100MHz system clock as an example, the delay accuracy is only 10ns, and high-precision delay simulation cannot be performed

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