Semiconductor Package Structure
A packaging structure and semiconductor technology, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and semiconductor/solid-state device components, etc., can solve the problems of increasing manufacturing costs, poor bonding force and adhesion, and reducing the reliability of semiconductor packaging structures. Achieve the effect of improving reliability and preventing breakage
Inactive Publication Date: 2017-04-12
MEDIATEK INC
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Problems solved by technology
[0003] However, while utilizing PoP and / or WLP technology to manufacture semiconductor packages, some issues may arise
For example, when performing a dicing process to produce individual package structures, the polymer-containing interconnect layer (sometimes referred to as RDL (Redistribution Layer, Redistribution Layer)) formed in the package structure may contaminate the mechanical saw (mechanical saw), and this cutting may also cause interconnect layer cracks
Therefore, increased manufacturing cost
In addition, in the manufacture of semiconductor packages, insufficient bonding force for die attachment and poor adhesion between the molding compound and the vias in the molding compound can reduce the reliability, yield and throughput of the semiconductor package structure
Method used
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[0025] The following description is for the purpose of illustrating the general principles of the invention only, and should not be considered limiting. The scope of the invention can be determined with reference to the appended claims.
[0026] The present invention is described with reference to particular embodiments and certain drawings but the invention is not limited thereto and only by the claims. The drawings described are schematic only and are not limiting. In the drawings, the size of some of the elements is exaggerated for illustrative purpose and is not drawn on scale. The dimensions and relative dimensions in the illustrations do not correspond to the actual dimensions in practice of the present invention.
[0027] figure 1 is a schematic cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present invention. In some embodiments, the semiconductor package structure 10 is a wafer-level semiconductor package structu...
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A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a first opening aligned with the dicing lane region. The semiconductor package structure of the embodiment of the present invention has a better reliability.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a fan-out wafer-level packaging structure with high reliability. Background technique [0002] In recent years, as electronic products have become more functional and scaled down, manufacturers of semiconductor devices are expected to form more devices on a single semiconductor wafer so that Electronic products are more compact. As a response to this hope, PoP (Package-on-Package, package-on-package or package-on-package) technology and WLP (Wafer Level Package, wafer-level packaging) technology have been developed. PoP technology enables two or more packages to be mounted (ie, stacked) on top of each other using a standard interface between them, allowing signals to be routed between them. This approach allows electronic products to have a higher component density, such as mobile phones, personal digital assistants (Personal Digital Assistant, PDA) and digital cameras. ...
Claims
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IPC IPC(8): H01L23/31H01L23/52H01L23/528
CPCH01L23/31H01L23/3107H01L23/52H01L23/528H01L2924/37001H01L21/561H01L21/568H01L23/562H01L24/19H01L24/20H01L24/96H01L24/97H01L2224/04105H01L2224/12105H01L2224/2919H01L2224/32225H01L2224/73267H01L2224/9222H01L2225/1035H01L2225/1041H01L2924/1431H01L2924/1432H01L2924/1436H01L2924/3511H01L2924/3512H01L2224/29016H01L2924/35121H01L23/544
Inventor 刘乃玮林子闳彭逸轩萧景文黄伟哲
Owner MEDIATEK INC