Recess array device

Abstract

The invention discloses a recess array device. The recess array device includes a semiconductor substrate and at least an active area in a main surface of the semiconductor substrate. A gate trench penetrates through the active area. The gate trench includes a first sidewall, a second sidewall facing the first sidewall, and a bottom surface extending between the first and the second sidewalls. A bump portion is disposed in the gate trench. The bump portion has two opposite sidewalls and a top portion extending between the two opposite sidewalls. A gate oxide layer is formed in the gate trench. The gate oxide layer has a first thickness on the first and second sidewalls, a second thickness on the two opposite sidewalls of the bump portion, and a third thickness on the top portion of the bump portion. The first thickness is greater than the second thickness. The second thickness is greater than the third thickness.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a recessed array device and a manufacturing method thereof. Background technique [0002] The trend in the memory and semiconductor industry for many years has been to continuously reduce the size of memory cells to increase the integration and storage capacity of DRAM chips. With the increase of the density of memory cells in the memory device, the recessed array device fabricated in the concave portion of the semiconductor substrate is also more and more popular. [0003] In general, a recess (or gate trench) formed on a substrate has opposing sidewalls and a bottom surface extending between the sidewalls. A gate oxide layer is firstly formed in the recess, the gate structure is then deposited into the recess, and then a doped region is formed on the main surface of the substrate to form a source and a drain. [0004] Prior art recessed array devices still have some disadvantages. F...

AI Technical Summary

Problems solved by technology

In the above overlap region, GIDL current may be caused by band-to-bandtunneling effect and cause operational limitation and loss of retention time performance for thin oxide memory cell devices

Although the GIDL current in the above overlapping area can be alleviated by increasing the thickness of the gate oxide layer, on the other hand the write-back performance will be affected

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