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IP core optimization method and device for multiprocessor system
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A technology of multi-processor system and optimization method, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of unable to obtain the same performance IP core and so on
Active Publication Date: 2020-05-01
SHENZHEN BOJUXING IND DEV
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[0008] The purpose of the embodiments of the present invention is to provide an IP core optimization method for a multiprocessor system, aiming at solving the problem that IP cores with the same performance and optimized area cannot be obtained when each IP core is mapped to a multiprocessor system
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Embodiment 1
[0034] figure 1 It is an implementation flowchart of the IP core optimization method of the multiprocessor system provided by the embodiment of the present invention, and is described in detail as follows:
[0035] In step S101, the compromise curve points of multiple IP cores are obtained;
[0036] Wherein, step S101 is specifically:
[0037] Obtain the trade-off curve of each IP core;
[0038] The trade-off curve is sampled to obtain the trade-off curve points for each IP core.
[0039] In step S102, different combinations are performed on the compromise curve points;
[0040] In step S103, the different areas occupied by the IP core during different combinations are extracted, and the area is the area required for mapping the IP core to a multiprocessor system;
[0041] In step S104, the different areas occupied by the IP cores are sorted to obtain the largest area IP cores and the remaining area IP cores;
[0042] In step S105, run the IP core with the largest area to...
Embodiment 2
[0052] figure 2 It is the implementation flowchart of the IP core optimization method step S104 of the multiprocessor system provided by the embodiment of the present invention, and is described in detail as follows:
[0053] In step S201, the different areas occupied by the IP cores are sorted according to the order of areas from large to small or the order of areas from small to large, to obtain the IP core with the largest area;
[0054] In step S202 , among all area IP cores, the IP core with the largest area is eliminated to obtain the remaining area IP cores.
Embodiment 3
[0056] The embodiment of the present invention describes the composition of parameter types, which are detailed as follows:
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Abstract
The invention is suitable for the field of multi-processor systems and provides an IP core optimization method and apparatus for a multi-processor system. The IP core optimization method for the multi-processor system comprises the steps of obtaining tradeoff curve points of a plurality of IP cores; performing different combinations on the tradeoff curve points; extracting different areas occupied by the IP cores during different combinations, wherein the areas are areas required for mapping the IP cores to the multi-processor system; sorting the different areas occupied by the IP cores to obtain the IP core with the maximum area and the residual area IP cores; running the IP core with the maximum area to obtain first performance parameters, and running the residual area IP cores to obtain second performance parameters, detecting whether the second performance parameters are same as or similar to the first performance parameters or not, and if the second performance parameters are same as or similar to the first performance parameters, setting the area IP core, which runs currently, as an optimized IP core. By optimizing the IP core, a large amount of required areas are reduced on the premise of realizing the same performance, so that the cost and the development expense are reduced.
Description
technical field [0001] The invention belongs to the field of multiprocessor systems, and in particular relates to an IP core optimization method and device for a multiprocessor system. Background technique [0002] In recent decades, since there has been a gap between software design and hardware design, that is, software design is always faster than hardware design, people are now moving towards using high-level synthesis (HLS) to speed up hardware design. Because the hardware design needs more time to debug, or needs to produce IP cores with different areas. [0003] Using high level synthesis (High level Synthesis-HLS), software tools (such as Cyberworkbench) can be used to convert high-level language IP cores (such as C, C++, SystemC) into behavior description language IP cores (Verilog HDL, VHDL). Can obtain different area (different performance) behavior description module (RTL) without changing the content in high-level language IP core by using different restriction...
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