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Many-core network processor and micro engine message scheduling method and micro engine message scheduling system thereof

A technology of network processors and scheduling methods, applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve problems such as difficult implementation, complex mapping, timeout retransmission, etc.

Active Publication Date: 2017-05-03
SANECHIPS TECH CO LTD
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Problems solved by technology

[0008] Secondly, the mapping between packets and microengines is also a complex problem. There are many mapping algorithms proposed so far, but most of them can only improve one aspect or the algorithms are too complicated to be implemented on hardware. Among them, the packets between the same data flow have the locality of the upper layer application, and it is necessary to ensure the order of the packets entering and leaving the network processor as much as possible to avoid the timeout retransmission of the upper layer of the network

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  • Many-core network processor and micro engine message scheduling method and micro engine message scheduling system thereof
  • Many-core network processor and micro engine message scheduling method and micro engine message scheduling system thereof
  • Many-core network processor and micro engine message scheduling method and micro engine message scheduling system thereof

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[0159] Although in the above description, the organizational structure of the microengine is fully parallel, another advantage of the present invention is that it can support a serial organizational structure at the same time. For a long time, in commercial network processors, the serial micro-engine structure is a mainstream architecture, which has the advantages of guaranteed performance and no disorder. The implementation case that the present invention realizes serial structure is as follows:

[0160] All messages enter from the first cluster, and after processing, specify the next-level processing cluster number through the microcode. After the message leaves the first cluster, in the routing module, specify the next-level processing cluster number according to the microcode The cluster number transfers the message from the next cluster, and so on until the message passes through all the clusters, and the message processing is completed. like Figure 7 shown.

[0161] ...

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Abstract

The invention discloses a many-core network processor and a micro engine message scheduling method and a micro engine message scheduling system thereof. The method comprises the following steps: when there is a message input, applying for a free pointer for the message; saving the message to a position to which the pointer points in a shared cache and saving the pointer to a corresponding stream queue, wherein stream queues are scheduled by means of round-robin scheduling; when the pointer in the stream queue is scheduled, looking for a micro engine corresponding to the pointer in order to map the message corresponding to the pointer to the micro engine; and when no micro engine corresponding to the pointer is found, saving the pointer to the corresponding stream queue again.

Description

technical field [0001] The invention relates to network processor technology, in particular to a message scheduling method and system for a many-core network processor and its micro-engine. Background technique [0002] The network processor is the core component of the forwarding plane in the field of data communication. It is a solution that takes into account the speed of the processor and the flexibility of use. It can flexibly modify the business microcode to meet the needs of various basic and complex network services. Business expansion and upgrade. [0003] Due to the rapid development of network services, the requirements for the processing capability of the network processor are getting higher and higher, and a single or a small number of micro-engines is far from meeting the processing capability requirements. The current solutions mainly include: increasing the main frequency of the system, increasing the number of cores and other methods. As for the method of ...

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Application Information

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IPC IPC(8): H04L12/751H04L12/803H04L12/863H04L45/02
CPCH04L45/02H04L47/125H04L47/50
Inventor 袁力
Owner SANECHIPS TECH CO LTD
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