Circuit for implementing transistor-level scheme of five-input-end combinational logic circuit
A combination logic circuit, transistor-level technology, applied in logic circuits, logic circuits with logic functions, electrical components, etc., can solve the problems of large transmission delay, large signal transmission delay, large silicon chip area, etc., to reduce the number of transistors. , the effect of silicon wafer area reduction
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[0016] Hereinafter, preferred embodiments of the present invention are given in conjunction with the drawings to illustrate the technical solutions of the present invention in detail.
[0017] Such as figure 1 As shown, the circuit of the transistor-level implementation scheme of the five-input combinational logic circuit of the present invention includes a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, and a fifth triode. The transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the thirteenth transistor Q10, the drain of the first transistor Q1 and the third The drain of the second transistor Q2 is connected, the gate of the first transistor Q1 is connected to the gate of the sixth transistor Q6, the source of the first transistor Q1 and the drain of the third transistor Q3 Connected, the gate of the second transistor Q2 is connected to the gate of the ninth transistor Q9, the source ...
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