Circuit for implementing transistor-level scheme of five-input-end combinational logic circuit

Abstract

The invention discloses a circuit for implementing a transistor-level scheme of a five-input-end combinational logic circuit. The circuit comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and the like, wherein a drain electrode of the first triode is connected with a drain electrode of the second triode, a grid electrode of the first triode is connected with a grid electrode of the sixth triode, a source electrode of the first triode is connected with a drain electrode of the third triode, a grid electrode of the second triode is connected with a grid electrode of a ninth triode, a source electrode of the second triode is connected with the drain electrode of the third triode, a source electrode of the third triode is connected with a drain electrode of the fourth triode, a grid electrode of the fourth triode is connected with a grid electrode of an eighth triode, and a source electrode of the fourth triode is connected with a drain electrode of the sixth triode. The circuit has the advantage that the number of transistors is decreased, so that the silicon wafer area occupied by same logic functions is reduced substantially.

Description

technical field [0001] The invention relates to a combinational logic circuit, in particular to a circuit of a transistor-level realization scheme of a five-input terminal combinational logic circuit. Background technique [0002] There are the following disadvantages and deficiencies in the current circuit for implementing the transistor-level implementation scheme of the five-input combinational logic circuit in the prior art: [0003] First, the circuit is complex and requires a large number of logic gates [0004] Prior art needs to realize logic Y=~((A·B)+C+(D·E)), compiled by hardware description language Verilog code, then after synthesis, it will be as follows figure 2 Shown: Called 2 inverters, 1 3-input NAND gate and 2 2-input NAND gates. [0005] Second, the signal transmission delay is large [0006] When the signal is transmitted through the three-level gate, due to the inherent delay of the gate itself, the total transmission delay from input to output incre...

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Problems solved by technology

[0005] Second, the signal transmission delay is large

The transmission delay from input to output is too large, and it will be fatal for circuits with high frequency, which are very concerned about the signal delay.

[0007] Third, the required circuit costs are high

[0008] Since the existing circuit uses 2 inverters (1PMOS+1NMOS, a total of 2 transistors), a 3-input NAND gate (3PMOS+3NMOS, a total of 6 transistors) and 2 2-input NAND gates (2PMOS+ 2NMOS with a total of 4 transistors), which generally requires 18 transistors. Due to the large number of transistors, the silicon chip area occupied by it is relatively large

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