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A Unified Colorer Array Multi-warp Instruction Fetch Circuit

A dyer and array technology is applied in the field of multi-warp finger fetch circuits in a unified dyer array, which can solve the problem of idle computing components, and achieve the effects of ensuring validity, flexible initial addresses, and simple fetch circuits and methods.

Active Publication Date: 2019-05-21
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0003] Therefore, in this case, the computing unit is idle for a long time

Method used

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  • A Unified Colorer Array Multi-warp Instruction Fetch Circuit
  • A Unified Colorer Array Multi-warp Instruction Fetch Circuit

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Experimental program
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Embodiment

[0061] like figure 1 As shown, a unified dyer array multi-warp instruction fetch circuit and method, including 8 warp pc address calculation unit, warp scheduling unit, instruction fetch information fifo and external icache.

[0062] The specific structure and function of each module are introduced in detail below:

[0063] The instruction fetch circuit includes 8 warps, each warp corresponds to a pc address calculation unit, and each warp has an independent instruction fetch pc address and a warp pc stack (which is used to realize the pc address when function nesting Save and restore), the size of each instruction fetch is 8 instructions, and each warp has a 2-line buffer cache;

[0064] The pc address calculation unit is used for calculating the warp pc address, and generates schedulable warp requests and warp pc addresses to the warp scheduling unit;

[0065] Among them, the schedulable warp request generation conditions are as follows:

[0066] 1) The warp cache can be ...

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Abstract

The invention belongs to the technical field of integrated circuits, and relates to a uniform stainer array multi-warp instruction fetching circuit and method. The circuit comprises a warp scheduling unit (1), instruction fetching information fifo (2), an external icache (3) and at least two warp pc address calculation units (4), wherein each pc address calculation unit corresponds to one warp. The multi-warp instruction fetching process can be realized, and latency of a memory is effectively hidden to improve the throughput capacity of a uniform stainer array.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a unified dyer array multi-warp indexing circuit and a method. Background technique [0002] The unified colorer array completes the unified coloring function of vertices and pixels. In the unified shader array, the instruction has a memory access instruction, and the subsequent instruction needs the result returned by the memory access instruction to access the memory. Because the memory access takes a long time to return, the operation unit has to stop and wait. After the memory returns the result, the following instructions can continue to run. [0003] Therefore, in this case, the arithmetic unit is idle for a long time. In order to make full use of the idle time of the computing unit, a multi-warp switching method is adopted to insert multiple instructions of other warps between such instructions of the warp to hide its memory access delay, so as to make full use...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/34
CPCG06F9/34
Inventor 魏艳艳田泽牛少平任向隆王宣明韩一鹏
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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