Method and device for generating RTL (Register Transfer Logic)-level IP (Intellectual Property) core

A nuclear method and nuclear device technology, applied in the field of RTL-level IP core method and device generation, can solve the problems of reducing area and failing to guarantee comprehensive performance, and achieve the effect of reducing area and ensuring comprehensive performance

Active Publication Date: 2017-05-24
SHENZHEN BOJUXING IND DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The present invention provides a method and device for generating an RTL-level IP core, aiming

Method used

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  • Method and device for generating RTL (Register Transfer Logic)-level IP (Intellectual Property) core
  • Method and device for generating RTL (Register Transfer Logic)-level IP (Intellectual Property) core
  • Method and device for generating RTL (Register Transfer Logic)-level IP (Intellectual Property) core

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Embodiment 1

[0029] figure 2 The implementation process of the method for generating an RTL-level IP core provided by this embodiment is shown. For the convenience of description, only the parts related to this embodiment are shown, and the details are as follows:

[0030] In step 201, a high-level synthesis is performed on the high-level language program to obtain multiple behavior-level IP cores.

[0031] In step 202, a trade-off curve of each behavior-level IP core is obtained, and the trade-off curve is a relationship curve between the area of ​​the behavior-level IP core and the amount of tasks. Among them, the task amount is the derivative of the delay.

[0032] In specific implementation, step 202 can be divided into the following three sub-steps:

[0033] A. Configure multiple restriction files. Wherein, the sub-step of configuring multiple restriction files is specifically: configuring multiple restriction files according to reducing the number of functional device restriction...

Embodiment 2

[0049] Embodiment 2 of the present invention provides a device for generating an RTL-level IP core, such as image 3 As shown, a device 30 for generating an RTL-level IP core includes a behavior-level IP core acquisition module 310 , a compromise curve acquisition module 320 , a preferred RTL-level IP core acquisition module 330 and a data structure netlist acquisition module 340 .

[0050] The behavior-level IP core acquisition module 310 is configured to conduct high-level synthesis of high-level language programs to obtain multiple behavior-level IP cores.

[0051] The trade-off curve obtaining module 320 is configured to obtain a trade-off curve of each behavior-level IP core, where the trade-off curve is a relationship curve between the area of ​​the behavior-level IP core and the amount of tasks.

[0052] The preferred RTL-level IP core acquisition module 330 is configured to acquire the preferred RTL-level IP core corresponding to each behavioral-level IP core according...

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Abstract

The invention provides a method and a device for generating an RTL (Register Transfer Logic)-level IP core, and belongs to the field of application specific integrated circuits. The method comprises the following steps that: firstly, carrying out high-level synthesis on an advanced language program to obtain a plurality of behavior level IP cores; then, obtaining the compromising curve of each behavior level IP core, wherein the compromising curve is the area and task load relation curve of the each behavior level IP core; according to the compromising curve, obtaining an optimized RTL-level IP core corresponding to each behavior level IP core; and carrying out physical synthesis on all optimized RTL-level IP cores to obtain a data structure netlist. Through the method and the device for generating the RTL-level IP core, each obtained optimized RTL-level IP core has an optimal performance ratio, and an area is reduced while overall performance is guaranteed.

Description

technical field [0001] The invention relates to the field of application-specific integrated circuits, in particular to a method and device for generating an RTL-level IP core. Background technique [0002] In recent decades, since there is a gap between software design and hardware design, that is, software design is always faster than hardware design, people are now moving towards using high-level synthesis to speed up hardware design. Because the hardware design needs more time to debug, or needs to generate IP (Intellectual Property, ASIC chip intellectual property) cores of different areas. [0003] Using advanced synthesis, you can use software tools (such as Cyberworkbench) to convert IP cores in high-level languages ​​(such as C, C++, SystemC) into IP cores in behavior description languages ​​(Verilog HDL, VHDL). The advantage is that you can use different restriction files (FCNT) to obtain RTL (Resistor Transistor Logic, resistance transistor logic) level modules w...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 许思源叶媲舟黎冰涂柏生
Owner SHENZHEN BOJUXING IND DEV
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