Synchronous reset D trigger for preventing single event upset

An anti-single-event, trigger technology, applied in pulse technology, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability, and achieve the effect of improving anti-single-event flipping ability

Active Publication Date: 2017-05-24
SHENZHEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] An embodiment of the present invention provides a synchronous reset D flip-flop that is resistant to single-event upset, aiming to solve the problem that the anti-single event upset capability of the synchronous reset D flip-flop is not high in the prior art

Method used

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  • Synchronous reset D trigger for preventing single event upset
  • Synchronous reset D trigger for preventing single event upset
  • Synchronous reset D trigger for preventing single event upset

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Embodiment Construction

[0023] In order to make the purpose, features, and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0024] see figure 1 , figure 1 It is a schematic diagram of the circuit structure of the C unit circuit based on the DICE structure, and the C unit circuit based on the DICE structure includes:

[0025] A first signal input terminal IN1, a second signal input terminal IN2, a signal output terminal OUT, a P-channel MOS transistor MP1, a P-...

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Abstract

The invention is suitable for the technical field of D triggers, and provides a synchronous reset D trigger for preventing single event upset. The D trigger comprises: a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, and both of the master latch and slave latch are dual mode redundancy reinforcement latches. Compared with the prior art, in the synchronous reset D trigger provided by the invention, the buffer circuits are added in front of the master latch and slave latch, so the single event upset ability of the synchronous reset D trigger is improved, dual mode redundancy reinforcement is carried out on the master latch and slave latch, namely the master latch and slave latch are separated to a pull up PMOS tube and a pull down PMOS tube in a C2MOS circuit, which are redundant to each other, therefore a possible feedback circuit caused by single event transient pulses is avoided, the C2MOS circuits in the circuits of the master latch and slave latch are improved, clock signals control the circuits through SMOS transmission rates, and the single event upset ability of the synchronous reset D trigger is further improved.

Description

technical field [0001] The invention belongs to the technical field of D flip-flops, in particular to a synchronous reset D flip-flop resistant to single-event reversal. Background technique [0002] There are a large number of high-energy particles (protons, electrons, heavy ions, etc.) in the universe. After the sequential circuit in the integrated circuit is bombarded by these high-energy particles, the state it maintains may be reversed. This effect is called the single event reversal effect. The higher the LET (Linear Energy Transfer) value of the bombardment IC, the easier it is to produce single event upset effects. After the combined circuit in the integrated circuit is bombarded by these high-energy particles, it is possible to generate a transient electric pulse. This effect is called the single event transient effect. The higher the LET value of the single particle bombarding the integrated circuit, the longer the duration of the generated transient electric pulse...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/3562
CPCH03K3/3562
Inventor 贺威贺凌翔张准骆盛吴庆阳
Owner SHENZHEN UNIV
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