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Hybrid processor framework and task scheduling method thereof

A processor architecture and task scheduling technology, applied in the direction of electrical digital data processing, instruments, program startup/switching, etc., can solve the problem of insufficient processing speed of reconfigurable devices, and achieve high-efficiency processing and high-efficiency effects

Inactive Publication Date: 2017-06-09
WUHAN UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The current research and implementation mainly focus on how to manage and optimize the reconfigurable device itself, but because the processing speed of reconfigurable devices is not efficient enough for general tasks, reconfigurable devices often need to cooperate with general-purpose processors , to complete the task processing together

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  • Hybrid processor framework and task scheduling method thereof
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Embodiment Construction

[0042] In order to further understand the present invention, the preferred embodiments of the present invention are described below in conjunction with examples, but it should be understood that these descriptions are only to further illustrate the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0043] A hybrid processor architecture and a task scheduling method thereof, the specific implementation flow of which is as follows.

[0044] 1) Hybrid structure of general-purpose processors and reconfigurable devices

[0045] Reconfigurable devices are the basis for reconfigurable computing research. Reconfigurable devices contain a large number of configurable logic cells connected together through internal networks. Since reconfigurable devices have the feature of dynamic reconfiguration, they can be used to accelerate specific applications while providing flexibility in application acceleration. However, since the re...

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Abstract

The invention discloses a hybrid processor framework and a task scheduling method thereof. The invention firstly provides a processor framework with mixing of a general processor and a reconfigurable device, and then a dispatcher is used for distinguishing a general task from a reconfigurable task; the general processor is used for processing the general task; the reconfigurable device is used for processing the reconfigurable task. According to the method, the cooperative processing of the reconfigurable device and the general processor is realized; different tasks can be respectively executed on the general processor and the reconfigurable device; the efficiency and the flexibility are higher.

Description

technical field [0001] The invention relates to the technical field of processor architecture, in particular to a mixed processor architecture and a task scheduling method thereof. Background technique [0002] Reconfigurable computing is regarded as an effective solution that can combine the high flexibility of traditional processors with the high processing efficiency of ASIC (Application Specific Integrated Circuit). Due to the good adaptability of the reconfigurable architecture, the processing speed can be accelerated through different granularities of parallelism for different applications. Among reconfigurable devices, FPGA (Field-Programmable Gate Array) is the most widely used reconfigurable device. Dynamically rechargeable and configurable FPGA is an important basis for realizing hardware-level multitasking. The processing area of ​​such FPGAs is usually divided into different sub-blocks. These sub-blocks belong to different hardware tasks. When a new hardware ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4881G06F9/5022
Inventor 王普章胡威郭宏蒋旻刘静戴文丽唐玉馨刘丹沈欢张瑜
Owner WUHAN UNIV OF SCI & TECH