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A kind of eutectic bonding method and semiconductor device

A eutectic bonding and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems such as leakage and affecting chip reliability, and achieve the effect of eliminating overflow

Active Publication Date: 2020-01-31
SHANGHAI IND U TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As shown in Figure 1(b), after the eutectic bonding is completed, a co-crystal bond formed by the first bonding material and the second bonding material is formed between the first bonding material pattern 11a and the second bonding material pattern 21a. At the same time, due to the effect of pressure and gravity, in eutectic bonding, the molten liquid alloy often overflows from the area where the first bonding material pattern and the second bonding material pattern are located to each part of the chip. At the place, overflow 4a is formed after cooling, and the overflow 4a is prone to leakage and other phenomena, thus affecting the reliability of the chip

Method used

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  • A kind of eutectic bonding method and semiconductor device
  • A kind of eutectic bonding method and semiconductor device
  • A kind of eutectic bonding method and semiconductor device

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Embodiment 1

[0041] Embodiment 1 of the present application provides a eutectic bonding method for bonding the first substrate and the second substrate into one body.

[0042] figure 2 It is a schematic flow chart of the eutectic bonding method in the embodiment of the present application, such as figure 2 As shown, the eutectic bonding method includes:

[0043] S101, forming a first bonding material pattern on the surface of the first substrate;

[0044] S102, forming a second bonding material pattern on the surface of the second substrate;

[0045] S103, forming a lower concave portion concave toward the surface of the second substrate in the second bonding material pattern;

[0046]S104. Align the first bonding material pattern with the second bonding material pattern, and press the first substrate and the second substrate under a predetermined pressure and a predetermined temperature, so that the first A substrate and the second substrate are eutectically bonded through the first b...

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PUM

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Abstract

The invention provides a eutectic bonding method. The method comprises the steps of forming a first bonding material pattern on a surface of a first substrate; forming a second bonding material pattern on a surface of a second substrate; forming a low concave part which is sunken in a way facing the surface of the second substrate in the second bonding material pattern; and aligning the first bonding material pattern to the second bonding material pattern, pressing the first substrate and the second substrate under predetermined pressure and predetermined temperature so that the first substrate and the second substrate are eutectically bonded through the first bonding material pattern and the second bonding material pattern. According to the method provided by the invention, the concave part is formed in the bonding material pattern of the substrate so as to accommodate alloy of a part of eutectic material during the eutectic bonding process, and an overflowing substance is reduced or eliminated.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a bonding method and a semiconductor device. Background technique [0002] Micro-Electronic-Mechanical-System (MEMS) packaging technology is an important research direction in the field of MEMS research. On the one hand, packaging can prevent MEMS products from being affected by dust, moisture, etc. Through vacuum or airtight packaging, the internal damping of MEMS products can also be changed to improve the performance of the products. [0003] Wafer-level packaging technology is the main solution to achieve high performance, low cost and mass production of MEMS products. Wafer-level packaging can be realized by using wafer-level keys and technologies. For example, adding a cover ( Cap) and bond the two to complete the package, so it has the advantage of batching and can reduce the cost of packaging. [0004] In wafer level bonding technology, eut...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/50
CPCH01L21/50H01L24/02H01L24/03H01L24/04H01L2224/02H01L2224/03H01L2224/04H01L2224/04105
Inventor 邱鹏张挺顾佳烨
Owner SHANGHAI IND U TECH RES INST